• Worked on External DDR Memory Interface IP for Agilex 5 and Agilex 7 FPGA families• Debugged RTL simulations to ensure IP compliance with JEDEC DDR memory standards• Expanded verification coverage in RTL simulations and FPGA hardware tests to improve long-term product health and stability for customers• Coordinated with multiple teams around the globe to resolve IP issues

• Verification of 800G Ethernet controller IP core• Modeled and verified design behaviour according to design specs using SVA and formal verification tools• Automated EDA tool flows and log file analysis using Python

• Wrote firmware in C for STM32 microcontrollers for interfacing with peripherals and subsystems using UART and SPI protocols• Debugged hardware communication using oscilloscopes and logic analyzers to verify signal values and signal integrity• Designed PCBs for an inertial measurement unit using Altium Designer, created schematics and wrote PCB documentation

• Verification of 800G Ethernet controller IP core• Debugged RTL simulations and coordinated with IP design team to fix issues• Analyzed functional and toggle coverage data to identify coverage holes in verification plan