Simon Yang Email & Phone Number

台灣 臺中市

Taichung City, Taiwan

1) Cross-function and cross-site process criteria alignment and standardization.2) CTQ list alignment for process control and monitor the process health.3) Deep diving on 8D, RMA and inline excursion with exploring new control points.4) Quality escape point investigation and enhancement on the detection point.5) Post assembly and post electrical test inspection consolidation for process control.6) Embed the CTQ list into FMEA and control plan as the process monitor.7) Network alignment and quality review for issues triggered from sites and OSATs.8) NPI Phase gate review for new product introduction.9) AIAG VDA pFMEA compliance and deployment.10) Change management control and review for any conversion.1) Control point hardening for escape points.2) FMEA and QCP alignment for CTQ lists.3) Establish business processes complied to global standards

Taichung City, Taiwan

1) Process setup for wafer preparation of PoP and 3DI assembly.2) Figure out the root cause and solution for the inline issues. 3) Find out the best process window and optimize process conditions.4) Yield detractor analysis for yield enhancement.1) Team leader for wafer preparation starting up of back grinding, dicing, laser DAF cut, die separation, and UV cure processes.2) Process window evaluation and optimization for WPH improvement. 3) FMEA and control plan deployment and management. 4) Assembly process development and yield enhancement5) Problem solving by applying DOE, FA, FMEA, 8D and SPC methodology.6) Cross-function and cross-site BKM alignment and fan-out activities.7) Coordinate audit activities for assembly processes and reply actions.8) Qualify new machines and new materials to achieve same quality requirement.1) WPH Improvement for processes.2) Die crack improvement by optimizing BG/SAW process parameters.3) NCF process and machine buyoff.4) pFMEA and control plan consolidation5) Process characterization for recipe standardization.6) ISO audit preparation.

湖口

1) In charge of STM WLCSP NPI.2) Provide technical assistance to the customer.3) New device SPEC discussion, evaluation and qualification 4) Assembly process development and yield enhancement 1) Communicate and identify the requirements with STM for all WLCSP devices.2) Coordinate with all modules to come out better conditions for mass production yield improvement activities.3) Yield analysis to figure out the failure root cause and DOE validation.4) Evaluate appropriate WLCSP process flow and conditions.1) Laser grooving evaluation for topside chipping improvement on low-K devices.2) Sawing parameter evaluation for backside chipping improvement.3) Magnification and ROI evaluation for AOI inspection4) MTT(Marking Through Tape) evaluation.

Singapore

1) Deliver health process for CMOS image sensor 2) Find out the best process window 3) Patents and Paper study to come out new ideas 4) New tools and materials survey 1) Co-work with STMicroelectronics to develop BSI CMOS image sensor device. 2) Coordinate with all modules to come out new idea for necessary process to implement Don the product. 3) Yield analysis to figure out the failure root cause and narrow down the split conditions. 4) Evaluate appropriate method to monitor inline abnormal. 1) Deep trench isolation structure evaluation2) White Pixel/Dark Current reduction project for photodiode

1) Adhesive converting process improvement. 2) Process issue solving 3) Yield enhancement 4) New materials implementation 1) OCA jumbo slitting, converting, inspection and packaging for OCA products.2) Operation manual preparation for new equipment releasing.3) BOM generation for all products.4) Unit cost calculation for all OCA products.1) Automaton slitter evaluation.2) SAP system implementation

1) BEOL process integration handling2) Figure out the root cause and solution for the inline issues. 3) Find out the best process window. 4) Analyze yield detractors for yield enhancement.5) New generation technology implementation. 1) 110nm Trench process Backend of line maintenance, March 2006 – September 2006 2) 90nm Trench process Backend of line process development, October 2006 - April 2007. 3) 90nm Trench process pilot run at the new 12” fab, August 2007 – February 2008. 4) 68nm Stack process pilot run, January 2009 – May 2009.5) 42nm Stack process pilot run, August 2010 – Feb 2011. 1) 2008 April, stack prose 68nm workshop in Singapore. 2) 2009 November – 2010 January, 42nm stack process transfer program in Boise U.S.A. 3) 2010 April, 42nm generation workshop in Singapore. 1) Negative PIQ implementation for stack DRAM process. 2) Al bond pad implementation.

Bachelor'S Degree, Chemistry And Material Engineering

Master'S Degree, Applied Sciences And Technologies