Tentative Thesis Title: "Configurable Architectures and Implementations for Ultra-Low-Power Edge Devices"MCU RTL Design: - X-HEEP: This project focuses on the design of the eXtendible Heterogeneous Energy-Efficient Platform (X-HEEP), an open-source RISC-V microcontroller to support the exploration of machine learning-based edge accelerators natively. MCU Silicon Implementations:- HEEPocrates - TSMC 65nm: The chip combines the X-HEEP microcontroller with a coarse-grained reconfigurable array (CGRA) and in-memory computing (IMC) accelerators.- HEEPnosis - TSMC 22nm: The chip combines the X-HEEP microcontroller with two new-generation IMC accelerators.- HEEPatia - TSMC 16nm: The chip combines the X-HEEP microcontroller with a new-generation CGRA and near-memory computing (NMC) accelerators. MCU FPGA Implementations:- Standalone: This project focuses on the implementation of the X-HEEP microcontroller on the programmable logic (PL) side of the Xilinx Zynq-7020 chip on the Pynq-Z2 board.- Linux-based: This project focuses on the implementation of the X-HEEP microcontroller on the PL side and the interaction with Linux on the processing system (PS) side of the Xilinx Zynq-7020 chip on the Pynq-Z2 board.Accelerator RTL Design:- GPGPU: This project focuses on the design of an ultra-low-power GPGPU for machine learning-based edge applications.

ASIC Design: - Teaching Assistant of Professor Adil Koukab at EPFL for the course ”Lab in EDA-based design” which focuses on the complete ASIC design flow, from RTL to GDS.FPGA Design:- Teaching Assistant of Professor Andreas Peter Burg at EPFL for the course ”Digital systems design” which focuses on the entry-level FPGA design flow, using Xilinx FPGAs.- Teaching Assistant of Professor David Atienza at EPFL for the course ”Lab on hardware-software digital systems co-design” which focuses on the design of complex HW/SW architectures on Xilinx FPGAs.

The Internship focused on the implementation and optimization of convolutional neural networks (CNN) on ultra-low-power heterogeneous multi-core architectures.

This project focuses on the development of open-source, configurable, and extendible RISC-V hardware. It is built around the eXtendible Heterogeneous Energy Efficient Platform (X-HEEP), a configurable and extendible RISC-V microcontroller designed to support the exploration of ultra-low-power edge accelerators. I started this project at the beginning of my PhD, and now it is an active part of my research activities. I am also responsible for managing the official “X-HEEP Platform” LinkedIn page.

The work focused on the development of low-level firmware to implement different functionalities of automatic test equipment (ATE). I also trained to use the complete laboratory equipment, including oscilloscopes, multimeters, wave generators, soldering irons, etc.