Pre-Si verification in a mixed OVM/UVM environment, transitioning to fully UVM.Verify training algorithms using constrained randomization, checker sequences (directed tests if needed), and assertions.Verify datapath using monitors, scoreboards, checkers, and assertions.Mixed-signal verification using VCS XA.Schematic (SPICE) vs RTL checking for behavioral models using Intel tool.Projects:Multi-Die I/O for Sapphire Rapids & Granite RapidsUCIe 1.0

[Digital IP Logic Design]RTL SystemVerilog designPre-Si verification using standard industry tools (VCS, Lint, CDC, etc.)Post-Si lab validation using Python and PerlRelease flow using git, svn, and turn-in checker toolsProjects:- DDR3/DDR4/LPDDR4 Combo PHY- PCIe 5.0 & Ethernet SERDES

Designed lab boards for Intel wireless adapter reliability testing.

Embedded systems projects for automotive products- Wireless winch controller- 4x4 to 4x2 hub switch controller

- Updated wiring & formboard diagrams for the wiring harnesses in Boeing CH-46 and CH-47 helicopters.- Created new diagrams for electrical systems for CH-46 upgrades.