- Built a scalable data analytics/machine learning framework in Python for SOC power grid integrity analysis

- Assist in porting Berkeley Analog Generator (BAG), a Python-based CMOS layout automation tool, to more advanced design processes- Advisor: Professor Vladimir Stojanovic

- Designed, validated, and simulated analog and digital circuit blocks in Cadence Virtuoso using Ayar Labs’ Python-based Arbitrary Cell Generator (ACG) to automate layout and schematic generation- Developed ACG infrastructure to simplify differential pair, bus, and ground-shielded routing for open-source use

- Led weekly discussion sections, wrote exam problems, and held office hours in EECS 16A, a course that covers analog circuits and linear algebra

- Implemented and tested an FSK demodulator on an FPGA with Verilog and Xilinx ISE that uses frequency mixers for channel selection, digital FIR bandpass filters for bit selection, and lowpass filters for removal of unwanted signals and envelope detection- Set up ADC and DAC interfacing for measurement and testing purposes- Designed PCB layouts for measurement and DAC boards using Altium Designer

- Conducted weekly small-group mentoring sessions to tutor students in EE 16A- Assisted in worksheet content creation- Guided Junior Mentors in improving their teaching abilities and mastering the course material

- Conducted economic modeling in Python for residential solar and solar-plus-storage systems; estimated customer savings using software company Genability's tariffs APIs- Simulated customer savings with potential changes to time-of-use rates- Provided potential policy and go-to-market strategies to provide customers with maximum savings through SunPower solutions