I'm Smitkumar. Passionate towards pursuing a career in VLSI design verification. I have completed a training of VLSI Frontend Design and Verification from VLSIGuru training institute, Bangalore.During my training I had worked on several projects. like AXI Protocol, AXI VIP Development, AHB UVC development and Universal memory controller Functional verification, have also done design projects of Interrupt controller, Watchdog timer, Patten detector and have good basics in Digital design, Verilog, System Verilog and Universal verification methodology(UVM).I would like to offer my service and express my interest in pursuing the career in same, you may contact me via LinkID message or email and I will be following up.Thank you....