Stefan Rusu Email & Phone Number

Sunnyvale, Ca, Us

Hsinchu, Taiwan, Tw

Santa Clara, California, Us

Led the technology and special circuits team for server processors:- Skylake server (14nm Xeon) - led the technology and clock distribution team- Ivytown (22nm Xeon) – led clock & power distribution, package interface, DDR I/O circuits team- Beckton (45nm Xeon) – responsible for clock distribution, power delivery, serial link circuits, leakage reduction activities- Tulsa (65nm Xeon) – led clock distribution, package interface, I/O circuits, leakage reduction- Madison (130nm Itanium) – drove clocking activities, packaging, floorplan evaluations for 9M- Merced (180nm Itanium) - clock distribution, power delivery, I/O buffers, package, thermalsRepresented server team in corporate-wide process and package technology developmentKey initiatives and technologies developed:- Proposed a chiplet-based 3D-stacked methodology for modular server processor design with improved yield and lower cost in the 10nm generation- Drove the silicon photonics package-level integration with server processors (2013-2015)- Led the team that delivered the Ivytown 1866 DDR3 and the first VMSE interface at Intel (2012)- Defined the I/O yield recovery for Ivytown processor (2010)- Drove the Ivytown I/O area compression for cost reduction (2010)- Proposed the core and cache yield recovery for servers (2007), proliferated to client processors- Developed the cache leakage shut-off technique (2005)- Headed the working group that developed the Serial VID voltage regulator technology (2004)- Led the Intel-wide leakage reduction working group (2002-2004)- Worked with TCAD to develop the first thermal map at Intel (1997)- Drove the first differential motherboard-level clock distribution at Intel (1996)

Interactive TV tiger team - an internal start-up initiative. Led a 10-engineer team on the definition, design and validation of a PCI-based video sampler and scaler processor

Owned the standard cell library development, bus interface unit, global clock distribution and power delivery, package design for two generations of SPARC processors. Managed 3 engineers on design and system debug activities.

Participated in circuit design, floorplan, layout, tape-out and silicon debug for several Ethernet controller projects.