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33 years experience in VLSI design and circuit technology development with special focus on server processors. Drove the implementation of multiple cost and power reduction initiatives, as well as package-level integration.IEEE Fellow since 2007 for "contributions to high performance microprocessor circuit technologies" 50 US patents issued, 95 papers and presentations in IEEE forums.
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Senior DirectorTsmcSunnyvale, Ca, Us -
Member Board Of DirectorsUniversal Chiplet Interconnect Express (Ucie) Jun 2022 - Present -
Senior DirectorTsmc Jul 2015 - PresentHsinchu, Taiwan, Tw
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Sr. Principal EngineerIntel Mar 1996 - Jul 2015Santa Clara, California, UsLed the technology and special circuits team for server processors:- Skylake server (14nm Xeon) - led the technology and clock distribution team- Ivytown (22nm Xeon) – led clock & power distribution, package interface, DDR I/O circuits team- Beckton (45nm Xeon) – responsible for clock distribution, power delivery, serial link circuits, leakage reduction activities- Tulsa (65nm Xeon) – led clock distribution, package interface, I/O circuits, leakage reduction- Madison (130nm Itanium) – drove clocking activities, packaging, floorplan evaluations for 9M- Merced (180nm Itanium) - clock distribution, power delivery, I/O buffers, package, thermalsRepresented server team in corporate-wide process and package technology developmentKey initiatives and technologies developed:- Proposed a chiplet-based 3D-stacked methodology for modular server processor design with improved yield and lower cost in the 10nm generation- Drove the silicon photonics package-level integration with server processors (2013-2015)- Led the team that delivered the Ivytown 1866 DDR3 and the first VMSE interface at Intel (2012)- Defined the I/O yield recovery for Ivytown processor (2010)- Drove the Ivytown I/O area compression for cost reduction (2010)- Proposed the core and cache yield recovery for servers (2007), proliferated to client processors- Developed the cache leakage shut-off technique (2005)- Headed the working group that developed the Serial VID voltage regulator technology (2004)- Led the Intel-wide leakage reduction working group (2002-2004)- Worked with TCAD to develop the first thermal map at Intel (1997)- Drove the first differential motherboard-level clock distribution at Intel (1996) -
Engineering ManagerPhilips Semiconductor Nov 1994 - Mar 1996Interactive TV tiger team - an internal start-up initiative. Led a 10-engineer team on the definition, design and validation of a PCI-based video sampler and scaler processor
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Senior Design EngineerSun Microsystems Nov 1988 - Nov 1994Owned the standard cell library development, bus interface unit, global clock distribution and power delivery, package design for two generations of SPARC processors. Managed 3 engineers on design and system debug activities.
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Design EngineerIntel Jun 1984 - Nov 1988Participated in circuit design, floorplan, layout, tape-out and silicon debug for several Ethernet controller projects.
Stefan Rusu Skills
Stefan Rusu Education Details
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Polytechnic University, Bucharest, RomaniaElectrical Engineering
Frequently Asked Questions about Stefan Rusu
What company does Stefan Rusu work for?
Stefan Rusu works for Tsmc
What is Stefan Rusu's role at the current company?
Stefan Rusu's current role is Senior Director.
What is Stefan Rusu's email address?
Stefan Rusu's email address is st****@****tel.com
What is Stefan Rusu's direct phone number?
Stefan Rusu's direct phone number is +140876*****
What schools did Stefan Rusu attend?
Stefan Rusu attended Polytechnic University, Bucharest, Romania.
What skills is Stefan Rusu known for?
Stefan Rusu has skills like Analog, Analog Circuit Design, Eda, Microprocessors, Circuit Design, Semiconductors, Soc, Asic, Embedded Systems, Vlsi, Mixed Signal, Ic.
Who are Stefan Rusu's colleagues?
Stefan Rusu's colleagues are Vivien Cheng, Cheng-Chang Chiang, 陳聿辰, Kareem S, 蔡瑞銘, Chamstein Wu, 林紜彤.
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