Sneha Bikumalla Email and Phone Number

IO timing and Constraints at chip level, Preparation of Constraints, scripts for Individual Interfaces, extensive checks and follow-ups with the design owners. Setup/Hold/Skew/Latency checks to be formulated.Good experience in RTL to Netlist of SOC design flow, worked on technologies below 10nm. Experience in low power and multi-voltage designs, resolving various timing, constraints issues. Collaboration and Interaction with various teams – RTL Design, Verification, DFT, PDOverview of all the IO Interfaces from a timing perspective- SPMI, SDCC, I2S, PCM, SPI, TIC, JTAG, I2C, PCIe, WIFI 2Gbps RGMII Ethernet, QDSS, Custom Asynchronous timings checks for AXI bridges, AHB bridges and PDXFIFOs.Top level constraint activities, Integrating block level constraints to top-level. Correctness and validity of the constraints, constraint demotion of the exceptions/clocks.Working closely with the STA/PD team on timing and constraint closure. Validity of the IO paths, high WNS and Half cycle paths are analyzed thoroughly.

RTL Design & Delivery for TLMM/Padring, and RTL Integration with SoC. SoC Floorplan Discussions for Predictive Convergence of Timing Critical Interfaces. IO Pre-Placement Guidelines to Timing ECO's at chip level. Timing analysis and convergence feedback.

The project used RADARSAT 2 data to map the wave structure of the ocean surface in agently sloping area with water depths ranging from 50 meters to the shore. The datawas used to determine the wavelength as well as the speed of progression of waves.These then were related to water depth using the gravity dispersion relationship forswell waves.

Summer Intern at Airport Authority of India, MumbaiAs a part of the curriculum, underwent summer training at Airport Authority of India(AAI), Mumbai and was familiarized with the different equipments and means used forproper communication navigation and surveillance of aircrafts which includes RADAR,HFRT (high frequency radio telecommunication), ASMGCS (Surface RADAR), transmittersand receivers.

Keyboard Interfacing with FPGA using Verilog HDLProject deals with the interfacing of the keyboard with Field Programmable Gate Array(FPGA). The keyboard was interfaced and the ASCII code was transmitted from LSB toMSB at the RS232 serial port of the PC through appropriate software (HyperTerminal) ina more efficient and user friendly way.