• Proficient in understanding the Design Specification.• Hands on experience in building test bench environment using UVM and SystemVerilog. • Familiar in working with SPI and I2C protocol.• Designed Sequence Detector, RAM, FIFO based on given Design Specification in Verilog.• Familiar with OOP’s Concepts in SystemVerilog.• Experience in developing Verification Environment for FIFO and AMBA-APB in SystemVerilog.• Developed multiple Testcases using Constrained Randomization for RAM, FIFO, AMBA-APB.• Proficiency in building self-checking test bench using SystemVerilog.• Familiarity of Linux working environment.• Clear understanding of ASIC design flow and logic design.. Familiar in Analog Layout. . Developed Flipflops,Latch block,Pulsr generator etc on The magic tool.