Shareef Mohd Email & Phone Number

Looking for a full-time opportunity | Graduated December 2018 from University of HoustonInterests: FPGA Design / ASIC Design/ SoC Design/Digital Design/Verification/Validation.VLSI designFPGA designVerification using SystemVerilogRandom TestbenchesAssertion-based verificationFunctional coverageUVMComputer Architecture - Pipelining conceptsVLSI testing and verification conceptsKnowledge of ASIC design flowHDL codingDRC, LVS, Parasitics extraction, Testbench simulations on cadence virtuosoSchematic Capture and LayoutRTL, gate-level netlist, Floorplanning, placement and routing, Static Timing Analysis, Clock tree synthesis conceptsSkills:Design Tools and IDE: Cadence Virtuoso, LTSpice, MATLAB, Quartus, ModelSim, ProteusLanguages: Verilog, VHDL, SystemVerilog, Python, C, C++, C#, R, Shell scripting, Tcl, Assembly Language, Embedded CFamiliar with UNIX / LINUXGithub URL: https://github.com/SOHAIL73824

Listed skills include Schematic, Altera Quartus, Cadence Virtuoso, Computer Architecture, and 27 others.