Sojan Thomas Email & Phone Number

• Experienced in ASIC IP Development/integration with a strong focus on Microarchitecture, RTL coding, synthesis, implementation, timing closure, and documentation.• Worked on protocols including USB4, USB 3.2, JESD204b, AXI4, HSDI, UART, as well as SPI, I2C, PIPE, IEEE 802.3 (1G PCS/PMA, 10G Base-R MAC+ PCS/PMA) and xHCI.• Proficient in SystemVerilog, Verilog, Tcl scripting, Shell scripting, Python, and IP-XPACT.• Hands-on experience with EDA tools such as Synopsys DC, Spyglass, JasperGold, VC Spyglass, Protocompiler, Synplify, Formality, VC Spyglass, VC Formal SEQ, Questasim, and VCS.• Recognized by peers for leadership and execution excellence, including winning the Shining Star award and the Live Wire award for outstanding performance.• Knowledgeable in linting, CDC/RDC analysis, multi-power domain design, and closure.• Familiar with project support tools like Perforce, JAMA, JIRA, and Code Collab.I'm open to discussing any challenging ASIC IP/SoC design roles that involve developing innovative and cutting-edge solutions. Let’s connect!