Sonali Dutta Email & Phone Number

Mountain View, Ca, Us

Build and serve Knowledge Graph.

Sunnyvale, California, Us

Working in the development of the Place and Route tool of Synopsys: IC Compiler.

Houston, Tx, Us

I worked on automata-theoretic program verification using assertions under the guidance of Prof. Moshe Y. Vardi.Research Project 1: Minimization of monitor generation and compilation time of CHIMP. (Dec 2011 - Feb 2013) - CHIMP is a tool for assertion-based dynamic verification of SystemC models, developed by Rice Verification Group. - Reduced the average size of CHIMP monitors by 61%, which also resulted in reduction of monitor runtime overhead by 8%. - Reduced the monitor generation and compilation time of CHIMP by 76%.Research Project 2: Improvement of the SystemC kernel patch used by CHIMP. (Feb 2013 - Mar 2013) - Upgraded an existing SystemC kernel patch of 1100 LOC that supports static monitoring of SystemC to a new patch of only 100 LOC that supports both static and dynamic monitoring.Master Thesis Project: (Apr 2013 - Dec 2013) - Developed \cplusplus package to monitor dynamic and concurrent flows in SystemC models. - Includes Flow Library, FLOWMONGEN tool, and Flow Monitoring Framework.

Santa Clara, California, Us

Project 1: Formal Equivalence Verification of FPGAs: - Codeveloped an RTL vs netlist formal equivalence verification flow for FPGAs consisting of an FPGA synthesis tool, Symplify, and a formal equivalence verification tool, Formality.Project 2: Intel Mobile Platform Testing: - Performed virtual platform boot testing, Android boot testing, USB testing and firmware testing on a future Intel mobile platform prototype.

Cambridge, Cambs, Gb

Project 1 (Testchip Team): Automation of physical design and verification flows. - Developed scripts to automate different aspects of the Testchip Physical Design Flow. These scripts significantly improved productivity and efficiency of the flow.Project 2 (Testchip Team): Physical design and verification. - Involved in Physical Design (RTL to GDS Flow) for Low Power design using CMOS Deep Sub Micron Technology.Project 3 (DA Team): Java CAD tool development. - Worked on development of CAD tool QABuilder that does quality analysis on different ARM products.

Master Of Science (Ms), Computer Science

Bachelor Of Engineering (Be), Computer Science