XR Graphics @ Meta Reality Labs (formerly, FRL - Facebook Reality Labs)- XR = eXtended Reality (AR/VR).- Low-power XR-performance graphics rendering pipelines and accelerators.- Microarchitecture, modelling, exploration and logic design.

I lead digital architecture and digital ASIC design initiatives. Role involved study of neural signal processing and delivering end-to-end silicon solutions towards Neuralink’s state-of-the-art Brain Machine Interfaces. - Low-power high-bandwidth real-time digital signal processing, inference and compression.- Digital and signal architecture, microarchitecture, logic and verification and firmware (silicon drivers and signal processing).

Full digital design cycle effort for digital cores and macros in TI’s DC/DC Controller and Converter products (commercial and automotive). Small low-area designs (<100k gates) in mixed signal environments. - Specification, architecture and logic design – ex: custom 1-wire/2-wire comms, pin-strapping, embedded memories with ECC, controllers for analog sub-systems (DAC/OSC/PWM), fault management, and control sequencers.- Metric driven functional verification (RTL/Gate in SVA), and stages of physical design – DFT and synthesis, formal verification, timing closure and power analysis.

Multiple responsibilities in the Tegra SoC Physical Design, with a primary focus on balancing performance with low-power constraints. Work involved the implementation of design methodologies, and development of EDA tools and automation systems for various facets of Physical Design.