 Currently a part of the post silicon validation team working on Intel’s Discrete Graphics and Client Products.  Involved in the post silicon validation of boot flow bringup for Graphics and PCH Die.  Wrote TAP based tests to boot different IPs and program functional and scan clocks at correct frequencies.  Converted the tests into tester compatible pattern and performed simulation during pre silicon phase.  Gained extensive working experience and knowledge of JTAG, IJTAG, boundary scan and internal scan.  Worked closely with DFT design team to understand TAP architecture and scan network.  Collaborated with Test Program teams to validate the patterns on the tester for High Volume Manufacturing.  Worked on 3 of Intel’s leading products, Ponte Vecchio, Meteor Lake and Lunar Lake.

 Designed blocks for a project from TR to tape-in on semi-custom circuit design (data path) to meet low power budgets along with aggressive timing targets.  Executed design convergence from RTL to GDS2 for partitions using Synopsys tools (DC and ICC2) by constraining designs to meet timing, power and area targets.  Achieved Timing Closure and Logic optimization of CPU core blocks.  Worked as a power owner for a section of the CPU and led the team towards meeting aggressive power targets.  Worked on Tiger Lake and Alder Lake projects along with silicon speed path fixes.