Spandana Rachamalla Email & Phone Number

Bengaluru, KA, IN

Bangalore

Development of EDA Tools and Methodologies for Power Analysis of pre-silicon Chip, Core and Unit.

• Involved in testing of low power verification tool for its functionality.
• Developed Verilog and VHDL test cases for various scenarios.
• Worked on voltage-aware simulation engine (MVSIM) and voltage-aware static checker (MVRC).
• Studied low power technology, verification complexities in multi-voltage designs and verification methods used in Synopsys.

Master'S, Computer Engineering, Digital Vlsi

Bachelor Of Engineering (B.E.), Electrical And Electronics Engineering

Graduated with Distinction, Aggregate of 86.6% Courses: Digital Electronics and Logic Design, Microprocessors, Power Electronics.