Rajath . Email & Phone Number

Bengaluru, Karnataka, India

I’m currently focused on block-level verification for a TenSilica SOC, emphasizing Functional and Connectivity testing. I’ve validated memory access, and verified front door and back door bootprocesses. Additionally, I’ve tested multi-master access to multiple slaves, using both serial and parallelaccess methods.Responsibilities:- Understand Block requirements and develop a test plan.- Developed UVM Test bench for the same.- Coded multiple tests in C and SV to cover all functional test.- Developed make-file for generating. different Hex file for CPU compiler.- Developed Code coverage and ran regressions for planned tests.- Led a team of five for this project.

Bengaluru, Karnataka, India

Verification of the PDC (Primary Decimation Chain) with various filter chains, adjusting filter coefficients to mitigate maximum noise suppression - Verified the connectivity test using Formal verificationfor block level.Responsibility:- Integrated assertions into formal verification at the block level.- Ran GLS to check timing violation for functional test

Bengaluru, Karnataka, India

SMBus is a two-wire interface often used for low-speed communication between deviceswithin a system, including Smart Batteries and other system and power management components.PMBusis an extension of SMBus, and is a low-cost protocol used for communication between power-managementdevices. PMBus was created as a power supply and semiconductor companies sought to redefine powermanagement within embedded systems, including creating a more efficient way to communicate withtheir power systems.Responsibilities:- Set Verification env to test Protocol bridge- Tested Various i3C features like With Different data speed.

Hyderabad, Telangana, India

IO pads, integral to System-on-Chip (SoC) design, act as the crucial link between thechip’s internal circuitry and external devices like memory, sensors, and communication interfaces. Thesepads are equipped with features such as voltage level shifting.Their purpose is to ensure dependable data transmission and compatibility with diverse voltage standards.Responsibilities:- Verified the differnet io pads w.r.t functionality and connectivity test.- leakage analysis with different voltage sequences, enable patterns for netlist blocks in finesim.

Worked on SystemVerilog real number modeling for both buck-boost converters and battery models. I have effectively integrated these models into high-level testbenches and conducted rigorous functional verification tests.