Responsible for clock analysis flow for SOC/IP, across most projects in AMD (CES). This includes flow/methodology development. Chips include Fusion, Server and Graphics. Drove, methodology convergence and adaptation of flow for many chips, with different clocking architectures and constraints, including MESH, TREEMESH structures, flow automation for improved productivity. Responsible for the SOC methodology for integration, clock extraction/simulation methodology, extraction for signal and overlay. Drive these activities, get closure on issues, and work with the customers (design) to understand the requirements, actively, look for new and improved methods. Provide documentation training and support when needed. Work closely with the designers to get initial execution for integration flow deployment.Develop & implement axe based prototype flow for integration for Roadrunner, in production for Llano/Orochi. This included learning all the details in the axe methods/flows, understanding the new requirements for the SOC method, writing prototype scripts and provide execution support for RR. Worked with Road runner design team to provide training for the new flow, and also support the flow Worked with CAD to get the required functionality in the axe flow including details definitions for the new flow.• Common flow for extraction and spice simulation for the full chip clocks. • DEF generation flow for integration and hardip. • DEF based clock & signal analysis.• Worked on 32nm and 28nm Chips, such as TN, LN, OR, KV,KT,TH.

Worked on Beckton (45 nm, 8 NHM core) processor, in the FC integration team. Flow development to production – Repeater insertion flow, non uniform routing grid generation & Power grid, M9 Power and hookup to Bumps for multiple power planes, Full chip routing, Physical netlist generation, Auto shield generation, Via insertion. Worked on L2 cache tail routing flows. Flows used to successfully tape out Aliceton (6 core 45 nm chip). Also responsible for delivering PI full chip builds. Involved in FC floorplan work & in top level timing closure. Work with the Design Technology team, NHM DA team & Aliceton DA /FC team.Worked on Dunnington project, which was using Penryn Core. Work in Penryn FCL team. Responsible for weekly FCL rollup based on the Merom flows. Successfully executed many rollups. Work with the section owners to facilitate Full chip weekly builds. Also work on FCL rollup flow improvements. Develop Parallel Rollup and mini-rollup for increased turn around time – 10 X improvements. Flows used to tape-out the first 45 nm Intel Chip.

Responsibilities include resource allocation, scheduling and management. Lead the physical design group from Netlist to Tape out. Work with the offshore groups to tapeout out chips. Work with third parties doing physical design.

Responsibilities include resource allocation, scheduling and management. Work with the other managers in the project. Tool evaluation, interface with tool vendors for tool support. Lead the physical design group in the following Floor planning including power planning.Place and Route including timing closure. DRC/LVS. Responsible for physical design and methodology for ‘Atom’ the Network processor Core (12M transistors) from netlist to GDSII (tape out). First silicon functional at 300 Mhz.Physical design methodology design and development for the future chips at Silicon Access, using hierarchical design methodology with over the block routing. Also responsible for other large blocks of the ‘IPP’ (network packet processor 170M transistors) chip functional at 300 Mhz.

Lead the physical CAD group in the following: Chip level integration tools. DRC/LVS. Place and Route tools for RLB's. Chip level integration tools and flows. Library development tools. Schematic entry tools.Key accomplishmentsMacrogen to production quality flow.Develop Chip level routing methodology. Specify the development of the automatic via generation tool. Specify the development of the bump placement and top-level power/clock grid generation tool. Design and implement abstract generation tool for data reduction. Design and implement section Build script.

Lead the Physical Design effort for ‘FORMIT’. Plan, design, architect and implement the ‘FORMIT’ placement tool. Architect the Physical design infrastructure for ‘FORMIT’ tool.Integration of the Placement with Optimization and Timing Analysis.

Lead the Global routing effort for ‘CHIP ARCHITECT’.Design and implement translation tools for ‘CHIP ARICHITECT’.Design the Routing representation for ‘PDEF’ 3.0 standard – now an IEEE standard

Developed a Relative placement tool for placing large number of custom blocks for PowerPC Microprocessor.Work with the design team in developing the internal tools.Worked on PowerPC 601, 620.

Responsible for development placement/partitioning algorithms implementation for ‘ARCCELL’.Succeeded in providing breakthrough technology for Std. cell placement.

Responsible for developing the pcell Compiler for ‘OPUS’ 4.0-4.2Worked on the ‘VIRTUOSO’ Layout Editor Features for ‘OPUS’ 4.0-4.2