Srikanth _ Email & Phone Number

Seeking a challenging Opportunity where I will be able to put my skills, work in project management with dedication, focus and strict adherence in achieving the organizational goals. I have always been a self-starter and I like to be responsible for my work. I'm confident that I'll be able to get the work done and meet deadlines. I also have excellent communicative and organizational skills. I'm a fast learner and I have a lot of curiosity about the world. As an internship trainee at ChipEdge, I worked on 4 Block level projects from Synthesis to Physical verification (DRC & LVS) using Synopsys EDA tools(Design compiler,ICC2,Prime-time,Star-RC & Formality ). I delved into the essential aspects of VLSI fundamentals and CMOS basics. My training encompassed critical phases in chip design, including Synthesis, Floorplanning, Power planning, Placement, Clock tree synthesis, Routing, Timing analysis, and Optimization. Additionally, I gained hands-on experience in physical verification and executed ECO (Engineering Change Order) flows. This comprehensive exposure equipped me with a strong foundation in the field of VLSI design.I like to use my skills to help people and make a difference. I have problem-solving and Analytical skills. I have always been able to take on challenges and I have a lot of initiative. I'm confident that I'll be able to get the job done and meet deadlines.

• 

  Physical Design Engineer

  Chipedge Technologies Pvt Ltd

  Jun 2023 - Present - Bengaluru, Karnataka, India

  Physical Design trained with four projects namely Chiptop, DTMF, FALCON, JBI. Good experience in RTL to GDSII of ASIC design flow – Synthesis, Sanity Checks, Floor planning, Placement, CTS, Routing, Signoff. Trained on design technology 28nm. Fixing the Pg_drc in the Power Plan. Physical Verification fixing LVS and DRV’s. Congestion analysis after the placement, improving congestions by placing various placement blockages. Floorplan has become major thing for better QOR. Performed Floorplan experiments to achieve a better Floorplan. Physical Design trained with four projects namely Chiptop, DTMF, FALCON, JBI. Good experience in RTL to GDSII of ASIC design flow – Synthesis, Sanity Checks, Floor planning, Placement, CTS, Routing, Signoff. Trained on design technology 28nm. Fixing the Pg_drc in the Power Plan. Physical Verification fixing LVS and DRV’s. Congestion analysis after the placement, improving congestions by placing various placement blockages. Floorplan has become major thing for better QOR. Performed Floorplan experiments to achieve a better Floorplan.