Srikanth Boinapalli Email & Phone Number

🔬 Experienced Analog Layout Engineer | Intel & TSMC Technodes Specialist | Driving IC Innovation 🔧👋 Hello! I'm a dedicated Analog Layout Engineer with 2 years of experience in the semiconductor industry. My hands-on expertise with industry-standard EDA tools like Cadence Virtuoso L/XL/GXL, Cadence PVS, and Mentor Graphics Calibre ensures precise and efficient layouts.🎯 My Expertise 🎯Reviewing floorplans and collaborating with circuit designers, I meticulously analyze intricate circuits to optimize performance. I excel in full instance generation and conduct thorough LVS, DRC, Antenna, and EMIR QC checks, guaranteeing flawless layouts.💼 Previous Achievements 💼In my previous roles, I specialized in custom layout for lower technology nodes, including Intel 7nm, 22nm, and TSMC 5nm, 16nm. My layouts have not only met design specifications but also contributed to enhancing overall circuit reliability.🚀 Driving IC Innovation 🚀As a knowledgeable professional in reliability concepts related to custom layout, I prioritize delivering robust and dependable designs. My in-depth understanding of layout electrical parameters ensures proper functioning and design closure.🌐 Join the Journey 🌐My excellent communication skills facilitate seamless teamwork, enabling collaboration with multi-functional teams to achieve exceptional results. Eager to learn and grow, I am excited to join Capgemini, where I can further expand my skills and contribute to the company's vision of creating groundbreaking IC solutions.If you're seeking an adaptable, results-oriented Analog Layout Engineer with hands-on expertise on both Intel and TSMC technodes, let's connect! Together, we can redefine analog layout engineering and shape the future of technology. #AnalogLayout #Semiconductor #EngineeringExcellence #CapgeminiCareers

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