Semiconductor professional with comprehensive experience in verification of complex ASICs (BT, WLAN , Network Controllers, Packet Processors, RISCV Sub-systems). Demonstrated ability to build and lead a team for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. Solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure. Exceptional manager with an ability to collaborate with global teams spread across different geography and time-zones.Currently leading design verification of connectivity subsystem (BT, BLE, HADM, UWB, 15.4) to Mobile, Automotive, IoT and Wearable markets. Specialties:SV/UVM, CFormal Verification CPU Sub-system (RISCV/ARM) and interconnect VerificationMulti Sub-system/Cluster Verification Low Power VerificationFPGA/silicon DebugExposure to RFA/V-Model simulationsComplex Sub-system Project management