Shriya Ate Email & Phone Number

1. Sr. DV Engineer at Radiant Semiconductors (client Tiwan Semiconductors)Roles & Responsibilities:-Tool - VCS.-Performing Unit delay simulation for checking UART, SPI, JTAG testcases.-Performing SDF simulation for checking UART, SPI, JTAG, testcases.-Debugging Timing issues.-Debugging X propagation using Synopsis verdi Tool. 2. DV Engineer at Capgemini Engineering (client Intel)Roles & Responsibilities:-Tool -VCS.- Cloning the model root & developing RTL build & GLS edits- Worked Zero delay simulation- Worked on SDF simulation- Force Conversion- Debugging Timing Violations (setup & hold)- Debugging X- propogation - Debugging Tool: Synopsys Verdi Holds a sound knowledge of,-Functional Verification- AXI, AHB, APB, SPI Protocol- HDL: Verilog,System verilog- HVL: UVM-Developing TB architecture -Functional and code coverage-Knowledge of working with linux OS

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  Rajiv Gandhi College Of Engineering And Research

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