Stacy Doss Email & Phone Number

Santa Clara, California, Us

Designed, developed and deployed a design verification flow based on Apache Airflow. The system is web based with a python backend for both job scheduling to a compute farm and the underlying web presentation and system control. During this project I was exposed to and became adept with several technologies that are employed by Airflow. These include, Flask, sqlalchemy, Jinja, D3, bootstrap JS, material icon usage, and others.

San Diego, Ca, Us

Developed and deployed flow management system used by approximately 5,000 design and verification engineers. System easily allowed users to use either pre-buillt flows or design custom flows using task based building blocks. For example a PnR flow may contain a place, cts and route task, each of which may contain several jobs to complete the task. This framework used a third party execution and resource package (FlowTracer) for integration with the company's compute farm. Developed a custom VIA generator with visualization. Developed a Calibre DRC editor that allowed selection and editing of various DRC files to target specific ECO activities. Developed a JIRA wrapper using REST calls to automate various task. Participated in group to standardize development process across EDA/CAD organization. Mentored various engineers in programming best practices, Agile Design Methodology, design patterns, test driven development, and other skill development areas.

Santa Clara, California, Us

Responsibilities included the architecture and development of ETL flows for various test stages of CPU, GPU and APU product lines. This included both highly flexible custom parsers written in perl and database design and implementation using MySQL. Develop highly customizable back-end applications with perl and R to visualize various trends in the manufacturing process, including WET and wafer sort. Provide client access to customization of both data collection techniques and trend visualization through a web interface using PHP, JSON, Javascript and HTML. Develop alternate data sets using MySQL for targeted reporting capabilities. Develop managed file transfer work flows to route data to internal and external consumers using Java, Apache ServiceMix, Camel, ActiveMQ with Eclipse, Ant and Maven.

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Integration engineer for the Open Modeling Coalition (OMC). Architected, designed and implemented Open Model Calculation Interface (OMCI) using C++, OpenAccess, Liberty, DCL and various perl and tcl scripts. OMCI is an open API for electrical model and design information. Specializations were developed for OpenAccess (OA), Liberty, ECSM, CCS and DCM. Participated as editor for IEEE 1481 version 2 which was adopted as an official IEEE standard in 2009. Used perl and XML for large scale document changes.

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Primary environment Linux, secondary Solaris. Main product was a rule based router using OpenAccess as the primary design database and C++ as an implementation language. As CAD/EDA software engineer designed and implemented interfaces for LEF, DEF, Spef, Oasis (GDSII), and Verilog. Designed and implemented RC extraction and timing engines. Designed and implemented centralized help system for interactive, HTML (with XML, XSLT and Javascript) and print documentation with source code generation. As product engineer, defined tool features, command set and user interface. Developed regression test for both unit and functional. Maintained Bugzilla bug tracking system for project management.

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Primary environment UNIX, secondary WinNT. Developed mission critical toolset for ASIC frontend and backend design. Used a combination of self developed perl applications, tcl and vendor specific scripting languages. Solved such problems as Verilog assign removal, automated timing closure, repeater insertion, and global edge rate improvement. Developed and implemented methodology for design flow including but not limited to floor planning, place and route (P&R), clock tree generation (CTS), in place optimization (IPO), RC extraction, delay calculation, design rule check (DRC), timing closure, signal integrity analysis (SI), engineering change orders (ECO) and logic equivalency checks (LEC). Design flow included such tools as PKS, Encounter, QX Fire & Ice, NanoRoute, Vendor Tools, Primetime, CeltIC, various vendor tools, and in house tools (COT). Developed methodology flow for design library creation and maintenance. Developed and implemented configuration and flow management tools for several different areas of the design process. Produced department wide programming practices including documentation, library use, design review, implementation procedures and qualification. Provided various application specific support tools and parsers, including Gate level verilog, DEF, LEF, Synopsys timing libraries, SDF and SPEF among others. Developed intranet web reporting and applications, such as, company wide Signoff Checklist and design flow checkpointing; using DHTML, JavaScript and DOM. Worked in a remote environment (TX) via telecommuting (CA).

Santa Clara, California, Us

Software lead for Product CAD group. Design and implementation of various software tools in support of debug, fault isolation, and production for current generation processors. Research and development of enhanced ATPG flow control, including non-destructive pattern generation for non-observable state points. Designed and implemented software infrastructure for Product CAD group. Developed both CAD and Engineering adaptable toolsets using perl, tcl, vendor and internal scripting languages. Integrated both internal and external software tools and data sets for Product group. Integrated various test equipment such as IMS-FT and Teradyne 971/973 with debug and failure analysis processes. Led effort to establish specific cross product Product CAD team in order to more effectively use resources and existing code bases.