UCIe-Compliant Die-to-Die adaptor IP for Chiplets Interconnect• Implemented a D2D adaptor that supports raw mode (AXI4) with ARB/MUX and CRC/retry capabilitiesacross different SoCs.• Completed the Adaptor Layer, Logical Physical Layer, and a Digital Analog Front End, which coherently executes the RDI bringup, param exchange, FDI bringup, and finally initiates data transfers.• A modular sideband implementation with universally programmable inputs, arbitration, and output broadcast capabilities• Provide robust link management and parameter exchange functionalities through different clock domains.• Develop IP RTL using Chisel and Verilog

Developer and project lead of Automotive Grade Automatic Test Pattern Generation (AG-ATPG) EDA flow, boosting chip testability and yield with physical fault models that target transistor level defects.- Enabled the company to meet ISO safety standards for manufacturing automotive-grade ICs.- Defined the roadmap for the future ATPG strategies with data from multiple SoCs.- Supported the server and AI-accelerator SoC teams for the AGATPG deployment.- Flow will be adopted by all future AMD SoC products for higher quality levels of chips.

Studied the chip architecture and timing resolution of multichannel digital photon-multipliers (MD-SiPM), and its application in positron emission tomography (PET). Duties include:• Programmed artificial neural network (ANN) model for time estimation with MD-SiMP.• Investigated the effects of hyper-parameters looked for the optimal values that results in lowest testing loss.• Studied the data-processing methods that leads to the estimation distribution.• Explored the ANN's physical limitations to implement on ASIC

Studied the design of elevator traffic system (ETS) using supervisory control of discrete event systems. Supervised by Prof. Murray Wonham. Duties include:▪ Designed the operation algorithm and the group control algorithm for ETS and wrote the corresponding timed simulation program using C++.▪ Developed discrete-event system (DES) model for ETS and combined the controlled function with its timed simulation results.▪ Programmed Python add-on modules and graphical user interface to optimize TDSUI, a software that constructs Discrete Event System models and computes their supervisory control functions.

Helped to develop and optimize the performance of neural networks, supervised by Prof. Parvaneh Saeedi. Works include:▪ Created programs to sort, anonymize, and organize files and datasets using Java and VBA.▪ Corrected AI-generated image data sets to improve the performance of neural network. Projects include: zygote-segmentation and classification, cloud recognition, and shadow recognition.