Stefano Traferro Email & Phone Number

Project leading for Gigabit Ethernet PHY in 32nm, 28nm and 28nm FDSOI technologies: macro + test chips development, SoC integration support.10+ year experience in the Data Storage world, developing HDD read/write channels from 180nm to 40nm technology nodes.My experience ranges from the digital design to the project management (from spec, through design and layout, to sign-off) in a high speed, low-power and aggressive schedule driven environment.Cross-functional, cross-site and cross-cultural communication and management skills have also been developed over the years and projects.2010 July-present: Project leading for Gigabit Ethernet PHY - team coordination and planning - design and test chip spec definition - top level integration, DFT design, STA constraint - P&R and sign-off support2009-2010 June: Project leading for HDD read-write channel in 40nm technology: - multi-site, cross-team management/coordination - third party technical interface for design definition and integration - design spec definition - top level integration and clock structure design - synthesis, layout hand-off and support, timing sign-off - application, testing and reliability support - customer support2007-2008: Project leading for HDD read-write channel in 65nm technology: - design spec definition - top level integration and clock structure design - synthesis, layout hand-off2004-2007: Project leading for HDD read-write channel in 90nm technology: - design spec definition - top level integration and clock structure design - synthesis - layout hand-off and support; timing sign-off - application, testing and reliability support - customer support2000-2003: Block level modeling, digital design, verification and synthesis.Main activities in digital filters (FIR and IIR), adaptive loops, top level control logic and clock structures.Specialties: design flow, RTL design, clock/DFT design, synthesis, timing analysis, project/team coordination

Listed skills include Dft, Semiconductors, Mixed Signal, Ic, and 12 others.

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  Universita' Politecnica Delle Marche

  Electronic Engineering