Provide a full support for IR Engineering Build Request (EBR) for new products for PowIR Block, IR-GAN (Gallium-Nitride wafer), and MOSFET.Conduct lot testing for engineering and qualification builds and other evaluation.Buyoff and verification of new hardwares - DUT Boards (Spike Check / GR&R /MSA), Handler Change-kits, Tester Upgrades.Handles process troubleshooting, product correlation, failure analysis, test qualification to meet set quality and yield.Ensure conformance of the test process based on set specification and defined guidelines, attainment of the optimum yield capacity, as well as high product quality and reliability.Responsible in sustaining continuous improvement in accordance to corporate goal.Operations and package conversion of test handlers such as HONTECH 9040, SRM XD248.Test Platforms: ETS 200FT,  TESEC 881T/TA, TMT ASL1K/3K

Achievement and Promotion• Promoted to Test/Product Senior Engineer – March 2010.• Promoted to Test/Product Engineering Section Head – March 2011.• Successfully qualified IDS Electronics as Test House partner of Texas Instrument Melaka(NS) – February 2011• Best Department: 5S and Quality – 2009, 2010, 2011• Merit of Accomplishment was given by International Rectifier for successfully setting up GYMS (Global Yield Management System) in IDS.• Successfully reduced the open-seal issue on TnR packaging.Duties and Responsibilities:• Provide a full support for test and product engineering requirement for different customer/client – National Semiconductor – Texas Instrument; Vishay Siliconix –HVM/HPP; International Rectifier, Advanced Monolithic Semiconductor, ICEMOS, Linear Systems, ST Micro, Cambridge Semiconductor, Taiwan Semiconductor, Imagis(Samsung) and Avago-Linaer RF.• Create and debug test programs for TESEC SPEKTRA 881T/TA DC tester.• Basic Credence ASL1000-TMT programming, load board design, and troubleshooting.• Usage of Teradyne A360 tester, troubleshooting and load board repair.• Test Yield monitoring and improvement.• Involved in Test production line process improvement.• Active participation on International Rectifier Global Yield Management System which includes definition of SBL and SYL for all device.• Knowledge and experience in doing Failure Analysis – Extrnal Visual Checking, Decapsulation, Etching, Cross-sectioning, Hot-spot analysis, and Die level inspection. • Established a quality audit check on a shiftly audit which involves product quality, 5S, and process compliance.• Review of build-sheet prior released to production.• Handles new material buy-off and qualification for packaging materials – carrier tapes / cover tapes / tube.• Task to create improvement on tape and reel quality.

Duties and Responsibilities Create and revise Spektra Test Programs for Tesec System to test different packages for various field effect transistors (FET). Create and revise Doilan Gate Charge and Gate Resistance test programs for various FETs. Review Assembly and Test Instruction (ATI) before releasing to production. Assembly yield improvement. Generate weekly Variance and Yield Report. JMP statistical data yield analysis. Weekly lot maverick device report. PPA/POA Projection. Completed phase1 of Global Yield Management System(GYMS) project. Assembly and Test Instruction generation and review.