Stephen Bowyer Email & Phone Number

Raleigh-Durham-Chapel Hill Area

Raleigh-Durham-Chapel Hill Area

Led design teams in the development of Embedded Computing Modules, which integrate FPGA and DRAM bare die onto a shared package substrate. Established a design flow and development milestones for System in Package (SiP) design. Published a white paper illustrating the power saving potential of SiP solutions. Investigated potential improvements in signal integrity for SiP solutions.

Defined chip architectures and led the design of high speed graphics DRAM products such as GDDR3 and XDR DRAM from initial feasibility/concept phase through product qualification/volume ramp. Interacted with development partners to define standard and customized memory chip solutions for customer applications. Designed a variety of analog and digital circuit blocks, including voltage generators, oscillators/timers, control logic and data paths.

Led the design of an innovation test-chip and coordinated the contributions of nine design teams across multiple sites in the US and Europe. Designed reusable voltage generators and developed test strategy and circuitry to characterize the performance in silicon. Developed test strategy and circuitry to characterize the performance of reusable high speed receivers, transmitters, and DLLs in silicon.Led the design of low power Mobile-RAM products and served as a primary technical expert… Show more Led the design of an innovation test-chip and coordinated the contributions of nine design teams across multiple sites in the US and Europe. Designed reusable voltage generators and developed test strategy and circuitry to characterize the performance in silicon. Developed test strategy and circuitry to characterize the performance of reusable high speed receivers, transmitters, and DLLs in silicon.Led the design of low power Mobile-RAM products and served as a primary technical expert at Infineon for low power DRAM design. Designed a variety of analog and digital circuit blocks, including voltage generators, oscillators/timers, receivers, transmitters, control logic and data paths. Show less

Led a design team in the development of a first generation DDR SGRAM product. Designed control and data path circuits, including the complete path from the DRAM core to receivers and off-chip drivers/transmitters. Implemented new features into the ALU of a 3D-RAM graphics memory product and verified functionality through Verilog simulation. Implemented an automatic place and route (APR) layout flow for memory products and trained layout engineers on proper usage and standard block… Show more Led a design team in the development of a first generation DDR SGRAM product. Designed control and data path circuits, including the complete path from the DRAM core to receivers and off-chip drivers/transmitters. Implemented new features into the ALU of a 3D-RAM graphics memory product and verified functionality through Verilog simulation. Implemented an automatic place and route (APR) layout flow for memory products and trained layout engineers on proper usage and standard block development. Completed physical layout of DRAM periphery circuitry. Show less

Ms, Electrical Engineering

Bs, Electrical Engineering