Stephen Camacho Email & Phone Number

Neubiberg, München, De

Design team lead and architect for multiple FRAM products. – First production capable 1T-1C FRAM which led to an ~40% array size reduction allowing a cost-competitive solution without new technology development.– First FRAM design implemented using “SOC design methodology” by creating reusable IP blocks and assembling as “chip + wires” enabling derivative product to be developed in a much shorter time.Lead architect and design lead for Radiation Hardened 512Mb Serial NOR Flash– First ever radiation hardened Flash products developed by IFXArchitect and design team leader for AI In-Memory Compute Tile for edge compute applications – First ever AI application of SONOS flash device by IFX– Compute Tile includes SONOS Multiply-Acccumulate-Macro, CPU, SIMD, input/output SRAM buffers, input/output staging buffers, etc.IP owner of digital and mixed-signal IP – Design tasks including RTL, synthesis, STA timing closure, LINT, CDC, DFT, verification, and verilog modeling– Power mode control, POR, clocks, testmode control, etc.

Fremont, Ca, Us

Participated in all phases of development from product definition through qualification.Responsible for digital design and verification of custom power management ICs. Digital design tasks including full-custom circuit design, RTL, synthesis, place and route, creation of verilog testbenches, and verilog modeling.Responsible for Design For Test implementation. Defined, reviewed, and implemented testability features ensuring test coverage of all circuits.Post-silicon debug and verification, including generation of PC based test programs/GUIs, and debug of production tests

Boise, Idaho, Us

Pre-silicon Verilog verification of 1G DDR3 DRAMPost Silicon debug and characterization of array/sense amp timing of 1G DDR3 DRAMBurn-in Test program development

Munich, ., De

Managed cross-functional multi-national team comprised of project managers, analog & digital circuit designers, and layout engineers which met or exceed goals every year.Expanded the department from 20+ to 50+ engineers with multiple social and corporate cultural backgrounds. Integrated all team members through team building, coaching, and cultural awareness establishing a flexible and highly creative engineering team.Drove methodology improvements within the development center and the world-wide organization resulting in reduced development efforts and higher visibility of project tracking.Key expert for IP creation and litigation in the world-wide organization with continuous involvement for over 9.5 years. Served as Qimonda representative for depositions in 3 separate IP infringement lawsuits in US Federal Court with the resulting outcomes saving millions of dollars. Established invention disclosure/patent procedure for development center and headed the site patent committee for 5+ years.

Neubiberg, München, De

Project Manager / Design team leader for multiple semiconductor memory products. Created project schedules, delegated work-packages, and tracked progress of project. Ensured proper risk-assessment, early communication of risks, and follow-ups in order to align activities with project time, cost, and quality goals. As part of the project core team, served as key representative of the development center to all other site/functions within the corporation, including product lines and manufacturing. Created highly engaged teams through team building activities, coaching, and cultural awareness. Planned, architected, and reviewed all technical aspects of design and layout. Successfully designed analog and full custom digital circuits, including I/O, voltage generators, reference circuits, array circuits, and control logic. Represented the development center on the world-wide design methodology council, which established the roadmap for the introduction of new design flows.

Cambridge, Ma, Us

U.S. Project manager / Design team leader for a custom DRAM product. Interfaced with the Japan team leader to communicate all technical and planning information, including transfer of all data to and from Japan. Guided US design/layout engineers in the development of the ALU portion of the product.Design and layout team member on multiple products, including standard, graphics, and custom DRAMs. Designed and verified full custom analog and digital circuits. Layout and layout verification from block level to full chip. Approximately 20% of time with company was spent working on-site in Itami, Japan.

Ms, Electrical Engineering

Bs, Electrical Engineering