Stephen Mcinerney Email & Phone Number

- Question-answering on pharmaceutical literature using Deep Learning- Chatbot development with Rasa NLU- Structured analysis of legal and patent filing documents- NLP: Text analytics, sentiment analysis, Information Extraction on reviews and social-media posts- NLP: text classification of customer logs, emails, IoT data, knowledge-base- Ontology/knowledge-base, NLP in foreign-language- Scraping of datasets (PDF, HTML, Excel, API)- Wearable dataset timeseries analysis, anomaly detection- Visualization- Python (pandas, spaCy, nltk, scikit-learn, PyTorch, word2vec, gensim, LDA), R

Redmond, Washington, Us

Developed Machine Learning offerings (NLP, R) for Azure cloud customers.- R API design for Machine Learning- Benchmarked performance on NLP datasets- Investigated featurization- Enabling out-of-the-box customer deployment

- NLP: extraction/IR of metadata from semi-structured legal text sources (Python, Java, SQL, Postgres, pylons, CoreNLP, nltk, WordNet) for pre-IPO SaaS client.- Predictive analytics for customer retention, segment analysis (R, SQL, Python, pandas, S3, ElasticSearch, REST, Magento API, data ingestion from multiple APIs and DBs). Achieved 1-5% lift in retention for multiple US clients (retail/social startups). Actionable business recommendations.- Text analytics: sentiment analysis of reviews, POS tagging- Structured document analysis (legal & patent filings), IR/tagging, NER- Sentiment analysis in social-media post corpus: segmentation, punctuation disambiguation, lemmatization across multiple languages, Unicode encodings- Search relevance of e-Commerce user queries- Visualizations with ggplot, pyplot, (timeseries, heatmap, marimekko plot) etc.- Analysis, visualization, geomapping of datasets (US Census/ACS, zipcode, pollution)- Online Handwriting Recognition with HMM (MSEE thesis)- Tools/technologies: bag-of-words, tfidf, word2vec, CoreNLP, NLTK, WordNet API, R tm, jython, POS, Named Entity Extraction, Semantic Types Identification- ML models: RF, logistic regression, GBM, XGboost, NB, HMM, feature selection, clustering- Github: bug reporter for Python pandas, sklearn, R dplyr, data.table, committer to h2o- Coursera NLP and ML courses, UCSC-Ext ML course

Palo Alto, Ca, Us

- Performance automation in Python of VMWare virtualization products. Successfully shipped Workstation 7.0 ahead of schedule- Regression triaging, test automation, visualization, custom builds, new test development, across Linux, Windows and Solaris VMs.- Web analytics on intranet

Palo Alto, Ca, Us

- functional verification, coverage-based methology, assertions, whitebox/graybox testing, random and directed test writing, Python automation, automatic XML-based test generation- languages: Python, XML, assertions, coverage (VCM & OVA),SystemVerilog/NTB/Vera- took Stanford CPD courses CS140 (Operating Systems), CS108 (OOP with Java), CS106X (C++), CS107 (Adv C++, Java, Scheme), CS143 (Compilers), EE108B

Mountain View, Ca, Us

- Sr PE for design automation software (Blast Create DFT, ASIC synthesis and Blast FPGA tools)- Blast Create ASIC synthesis , Verilog/VHDL high-level and physical synthesis, formal verification- Blast Create DFT: product engineering for DFT, scan insertion, scan physical optimization, ATPG.- Blast FPGA: high-level and physical synthesis targeting Xilinx Virtex, Actel ProAsic and Altera. - Responsible for product build testing, critical issue support, QOR suites, new feature specification, supporting customer benchmarks, solving DFT and QOR problems, writing and delivering customer training, user guides, application notes, AE field presentations, example Tcl scripts.- Interfaced with other groups: Optimization, RTL parser, Library, Timing, Placement, Clock Tree, Power Grid, Prototyping, GUI, QA, MTcl and Data Model.

- Architected QA of analog EDA software, and of CAD flow (90nm, 0.13um)- Successfully architected and implemented entire scalable, distributed, load-sharing QA infrastructure (Spectre + Mentor Calibre extraction + GRID + distributed Makefile + Python + PERL) for analog circuit signoff.- Raised productivity by 4000% through parallel Makefiling, Sun GRID distribution and transistor compaction.- Implemented CAD flow incl. netlisting, schematics, simulation, Calibre and Cadence physical verification.- Worked on two software engines and five tapeouts on various 0.18, 0.13um and 90nm technologies.- Troubleshooted Spectre, DRC, LVS, extraction and ruledeck issues.

Us

- Responsible for CAD support of all logic coding, synthesis, constraint scripting, timing, linting, power estimation, formal verification, library design and maintenance and LSF.Implemented reference flows and supported design teams. - Primary CAD interface to timing-driven P&R, floorplanning, clock insertion, DFT, ECO, emulation and verification.- Supported both CPU and ASIC methodologies for 3 tapeouts at 0.13um of Crusoe and Efficeon CPUs.

Msee, Electronic Engineering

Bsee, Electronic Engineering