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Senior Technical Staff Member, System Performance Lead for Power System Servers, a product line which consistently has world-leading system performance. Led 12 teams covering complete life cycle of development (concept, hardware performance analysis, product plan, system performance measurements, marketing, and field support) to collaboratively solve numerous challenges. Broad experience working with research, hardware engineers in logic design, circuit layout, power, packaging, and cooling and software engineers in compilers, hypervisor, operating systems, and databases to optimize system performance. PhD in electrical engineering with deep technical skills to solve the toughest technical challenges.
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Senior Technical Staff Member, System Performance LeadIbm May 2000 - PresentArmonk, New York, Ny, UsResponsible for all aspects of Power7+ system performance (processor design, product plan, benchmark measurement and publication, marketing messages, and field support). Hardware performance team lead on prior processors.Power7+ (announced Oct 2012)• In spite of a schedule slip, parts shortage, and lower than planned processor frequency, I managed system performance to beat the competition and provide a good gain over the prior design:• 20-40% more core performance than Power7 and 50% more cores in some models yielding even greater system performance gain• more than 40 industry-standard, leading benchmark publications• Overcame numerous performance issues which improved performance as much as 30%• Prevented several product plan or design changes which could have reduced performance as much as 20%• Drove product plan and design changes that improved performance by as much as 30%• Upon realizing that SPECint_rate performance would only be equal to competition, I drove compiler changes which resulted in a 15% performance improvement even though no changes were planned for this releasePower8 (not yet announced)• Analyzed 8 new design features eliminating performance bottlenecks and suggesting design changes that improved performance which, in some cases, changed the value of the feature from worthless to valuable. In other cases the feature couldn't be improved and it was eliminated due to the analysis.Power7• As the number of cores increases, the scalability of the software needs to be improved to utilize the hardware. This is a very difficult task that I worked on for many years with each new design. Power7 had 256 cores with 4 threads per core making scalability a huge challenge. I contributed significantly to achieving near linear scalability.Power6• My contributions to hardware and software scalability lead to achieving 6 M Transactions/min on the TPC-C benchmark which was ~50% higher than the competition.
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Senior Engineer, Hardware Performance Team LeadIbm May 1995 - May 2000Armonk, New York, Ny, UsLead the team which did performance analysis of the hardware. Also interacted with many software groups as well as being involved in the optimization of system performance.• The performance analysis of my team lead to 3 very successful designs being shipped during these years; Power4, A50, and A35• Recognized the memory wall before the research community did and drove multithreading as a solution. The A50 was the first commercially successful product to include this feature. This feature now provides up to a 100% performance gain on Power7; larger than any other feature. I received a corporate award for this work.Much of the work in the previous position was at the microarchitecture level. This work has included the concept-phase performance evaluation of many microarchitecture features to determine which features should be included in future designs. This position expanded that to continue through the implementation and eventual shipment of the product. This performance analysis included predicting the performance for concept evaluation, design definition, detailed design trade-offs, performance verification, competitive analysis, setting requirements, system design, and product planning. Of course, the input to this process is the analysis of workloads (of which I analyzed many), workload trends, shifts in language characteristics, and market trends. This work has also included the definition of hardware performance instrumentation and support for trace collection.In addition to the evaluation of major, microarchitecture features, I was involved in the system-level performance analysis of several processors and memory systems. This work has included all parts of the processor and memory system (memory systems, coherency protocols, caches, and processor microarchitecture).I have also proposed and been involved in joint research projects with the research division.
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Advisory Engineer, Hardware PerformanceIbm Sep 1990 - May 1995Armonk, New York, Ny, UsThis position is an extension of my previous position into more aspects of performance analysis.The processor designs that I worked on went into AS/400 systems (now part of Power Systems). With the conversion of the AS/400 to PowerPC architecture processors, this has expanded to include RS/6000 and SP2 products (now Power Systems).Initially, the AS/400 was based on processors with a proprietary, CISC instruction set architecture (ISA). I was heavily involved in the decision to convert the AS/400 to PowerPC architecture processors and was subsequently involved in the ISA extensions needed to make that conversion possible. This involved working with architects from several IBM sites and divisions. Later work included the evaluation of Very Long Instruction Word (VLIW) architectures to determine their performance advantage and feasibility.I was also instrumental in the proposal, evaluation, and definition of coarse-grained multithreading which eventually shipped in the A50 processor in 1997; the first successful processor to include multithreading. Following that, I continued to pursue this investigation into simultaneous multithreading (SMT). This was bleeding edge research. Intel has since called this Hyperthreading in their marketing literature. SMT was first included in the Power5 processor and showed up to 60% performance gain. SMT has been included in every Power Systems product since and on Power7 has shown up to 100% performance gain. My work on multithreading has been my biggest contribution to processor designs and I received a corporate award for it.
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Staff Engineer, Hardware PerformanceIbm May 1989 - Sep 1990Armonk, New York, Ny, UsI did performance analysis of processors, multiprocessors, and memory systems for AS/400 systems (now part of Power Systems). Among the more notable work was my heavy involved in the definition and evaluation of Non-Uniform Memory Access (NUMA) multi-processors. This was ground breaking research as there were very few papers published on the subject at that time.
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Staff Engineer, Hardware PerformanceIbm Aug 1987 - May 1989Armonk, New York, Ny, UsThe focus of this position was performance analysis of a vector facility for a mid-range, System/370XA product (now system z). This position involved doing performance analysis to predict the performance of the product and making design trade-offs, optimizing microcode for performance, working with compiler writers to get code optimized for the design, and working with the research division to get a hand-optimized library of engineering/scientific routines.
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Systems Design Engineer - TechnologistWestern Digital Sep 2013 - Nov 2022San Jose, Ca, UsProcessor and firmware performance.
Steve Kunkel Skills
Steve Kunkel Education Details
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University Of Wisconsin-MadisonElectrical And Computer Engineering -
University Of Wisconsin-MadisonElectrical And Computer Engineering
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University Of Wisconsin-MadisonElectrical And Computer Engineering
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Loras College
Frequently Asked Questions about Steve Kunkel
What company does Steve Kunkel work for?
Steve Kunkel works for Ibm
What is Steve Kunkel's role at the current company?
Steve Kunkel's current role is Senior Technical Staff Member, System Performance Lead.
What is Steve Kunkel's email address?
Steve Kunkel's email address is sk****@****ter.net
What is Steve Kunkel's direct phone number?
Steve Kunkel's direct phone number is +150732*****
What schools did Steve Kunkel attend?
Steve Kunkel attended University Of Wisconsin-Madison, University Of Wisconsin-Madison, University Of Wisconsin-Madison, Loras College.
What are some of Steve Kunkel's interests?
Steve Kunkel has interest in Woodworking, Books, Running, Movies.
What skills is Steve Kunkel known for?
Steve Kunkel has skills like Processors, Computer Architecture, System Architecture, High Performance Computing, Logic Design, Powerpc, Operating Systems, Unix, Debugging, Aix, Computer Hardware, Software Engineering.
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