Steve Lytle Email & Phone Number

Dallas, Texas

Analog Process Integration, RFAB. FEOL, BEOL, and analog device integration in TI's 300mm analog manufacturing fab.External Development and Manufacturing. Collaborate with foundry partners to develop 28nm digital CMOS technology distinctive to TI’s needs. Work with foundry to eliminate predominant defect mechanisms, including contact to gate shorts, contact opens, contact to contact filament shorts. Includes setting design rules, designing parametric test patterns, and risk analysis for the contact & pre-metal dielectric loop. Work primarily in MOL (middle-of-the-line) of technology, covering contact and pre-metal dielectrics. Preliminary 3-D modeling for MOL resistance and capacitance (RAPHAEL) for 20nm technology offerings. Internal 65nm Flash BEOL technology integration, including parametric test patterns & high voltage (erase gate) risk assessment.Responsible for integration and development of contact and pre-metal dielectric (PMD) loop for 65nm technology node. Optimized parametric data, reliability, and yield by designed experimentation. Solved several yield limiting problems including elimination of PMD gapfill issues by modification of FEOL STI oxide loss and sidewall spacer reduction, elimination of N+ contact outliers and opens caused by oxygen containing defects by optimization of NiSi thickness, contact etch, and post etch cleans Member of TI’s Interconnect and Post-Processing Patent committee for two years.

Leuven, Belgium

R&D assignee at IMEC in Leuven, Belgium. Metal hard mask dual damascene integration and materials characterization of porous low-k dielectric materials for advance IC technologies. Characterization and evaluation of Cu contacts for CMOS. Gave technical presentations to the low-k material vendor representing the IMEC team involved in characterization and integration. Skills include thin film dielectric constant measurement, nano-indentation for thin film mechanical properties, and capacitance modeling with RAPHAEL.

Allentown, Pennsylvania & Orlando, Florida

Distinguished Member of Technical Staff - Project leadership for development of low-k /Cu BEOL for 0.13µm tech, incl. selection of low-k film & damascene scheme, optimization of parametrics, reliability, and yield. Oversaw materials selection through yield improvement, passing burn-in and electromigration in 12 months! Key member of plant-wide contamination protocol team. Enhanced yield of 7-level Al and FSG-based BEOL for 0.14µm CMOS & 0.16µm technologies in manufacturing. Appraisal of yield limiting failure modes using failure analysis data and electrical defect density data testers.. Supported and consulted manufacturing facility in Singapore.Led development of 4/5-level BEOL for 0.25µm tech., incl. introduction of HDP gap-fill dielectrics, W-plugged contacts and vias, both oxide and W CMP into manufacturing. Technology transfer into Singapore fab.Technical Manager - Managed team for 0.3µm and 0.35µm eSRAM technologies, incl. development and qualification schedules, transfer into manufacturing (Madrid), interaction with design & manufacturing. Generated a team, hiring from both internal and external candidates, developed yearly objectives and appraisals, and coordinated team members’ responsibilities. Brought 0.35µm eSRAM technology to full qualification, including burn-in, HTOB, packaging and intrinsic reliability tests. Member of Technical Staff - Developed and transferred the gate, LDD, and S/D modules for 0.5µm and 0.35µm CMOS into manufacturing. Responsibility for Leff control, low defect density, high reliability, and manufacturability. Shared responsibility for design rules.Developed and patented via-level a-Si:H antifuse and processing technology for programmable logic. Device characterization, design rulesn, reliability characterization, and IC integration development.Designed and characterized sub- and near micron 4LM technology using CVD W & selective W plugs. Test structure design, electromigration testing, hillock studies,...

Mesa, Arizona

Senior Staff Engineer - Developed a sub-micron, four-level interconnect technology for the VHSIC Phase II program. Qualified for government "secret" clearance. With process engineering, integrated an SOG-based interlevel dielectric with a layered metallization structure; metal levels were interconnected with a W-plug technology. Designed test structures to characterize and optimize metallization reliability. Developed high power, high voltage analog metal gate and polysilicon gate biCMOS technologies incorporating a substrate power PNP output device, high voltage DMOS, with standard CMOS and bipolar devices. This technology was developed in a bipolar analog manufacturing line. Characterized plasma enhanced CVD oxide and nitride films. Investigated the water adsorption properties and polarization of polyimide films used as interlevel dielectrics. Studied, in detail, the usefulness of intrinsic and extrinsic gettering techniques in high voltage/power analog bipolar technologies.

Ms, Materials Science

Activities and Societies: Keramos Academic FraternityGPA: 4.00/4.00 Xerox Research Award for M.S. in Materials Science, July, 1981

Bs, Ceramic Science And Engineering

Activities and Societies: Keramos Academic FraternityGPA: 3.74/4.00