Steve Schauer work email
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Steve Schauer personal email
Engineering professional with experience in leadership roles and team contributor. Experienced HW Designer and Architect with a demonstrated successful history working in the semiconductor industry. Skilled in Hardware Architecture, RTL Design, embedded system, microprocessor subsystems, high speed interfaces such as SATA, SAS, PCIE/NVMe, UFS, Data Acceleration functions, Data Security (AES, RSA, ECC), Key Generation, Secure Key Storage, Testing, Simulation, Verification and Firmware (C++). Strong communications and presentation skills.
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Senior Asic ArchitectMicron Technology Apr 2021 - PresentBoise, Idaho, Us
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Staff Electrical EngineerSyncroness May 2020 - Apr 2021
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Hw ArchitectGoke Us Research Labs Jan 2018 - May 2020• Lead HW architecture and design of a scalable Data Accelerator and enterprise level NVMe SSD products. • Both designs utilized RISC-V processor cores, Network on Chip (NoC) IP, DDR, ONFI and Toggle NAND interfaces. • Products also incorporated Advanced Encryption Standard (AES), RSA, Secure Hash Algorithm (SHA), Elliptical Curve Coding, as well as data compression/decompression, Encryption key management/generation, key exchange, and secure key storage.
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Fw Architect / DesignerFlxsa, Llc Aug 2017 - Jan 2018UsDeveloped architecture for measuring various video compression algorithms. -
Sr. Asic DesignerKazan Networks Mar 2017 - Jul 2017Remotely designed and implemented, in an FPGA environment, a performance measurement module required for a PCIe-to-Ethernet Network SOC.
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Principle Architect / Asic DesignerMicron Technology Sep 2011 - Mar 2017Boise, Idaho, UsTechnical/Design lead for scalable SAS/SATA/PCIe SSD's.. Responsibilities include HW Design architecture, interface requirement development, RTL design, FW integration and training, as well as test, verification, and validation.
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Sr. Ip Design EngineerLsi, An Avago Technologies Company Jun 1997 - Sep 2011San Jose, Ca, UsDeveloped LSI’s SATA/SAS IP cores from concept through implementation into successful multi-customer ASIC programs. -
Hw Design Project LeadHoneywell Defense Avionics Systems Jun 1987 - Jun 1997Lead HW effort for the US Air Force F15E Digital Map System. Responsibilities included HW Architecture and testing. Management, scheduling and leadership role for 5 designers. Monitor design status, conduct hardware design reviews, correlating testing and firmware integration of the Digital Map System.
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Instrument EngineerTexas Instruments (Gsi) Jun 1981 - Aug 1984Instrument Engineer -Duties included the maintenance and calibration of seismic data computers, and other electrical components in remote desert sites. Supervised a crew of 90 individuals, many of whom could not speak English
Steve Schauer Skills
Steve Schauer Education Details
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Montana State University-BozemanElectrical And Electronics Engineering -
North Dakota State College Of ScienceElectromechanical Technology/Electromechanical Engineering Technology
Frequently Asked Questions about Steve Schauer
What company does Steve Schauer work for?
Steve Schauer works for Micron Technology
What is Steve Schauer's role at the current company?
Steve Schauer's current role is Staff Electrical Engineer at Syncroness.
What is Steve Schauer's email address?
Steve Schauer's email address is st****@****ron.com
What schools did Steve Schauer attend?
Steve Schauer attended Montana State University-Bozeman, North Dakota State College Of Science.
What skills is Steve Schauer known for?
Steve Schauer has skills like Application Specific Integrated Circuits, Testing, Rtl Design, Firmware, Hardware Architecture, C++, Systemverilog, Verilog, Sas, Serial Ata, Nvme/pcie.
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