This is a senior R&D engineering position, it requires a bachelors degree in Electrical Engineering and 5+ years experience working with ASIC design support. The main value added from this position is validation, characterization, and prototype development for SERDES IP, as well as taking a leadership role within an engineering team. The duties for this position cover a broad range of technical skills and tasks involved in supporting and debugging an ASIC design.The technical focus of this position is in ASIC IP for SERDES standards such as SATA Gen3, PCIe Gen3, and USB3.1 Gen2. Technical skills utilized include measurement and experimentation with of SERDES IP using lab equipment such as Lecroy SDA, Keysight JBERT, Keysight VNA. Other duties include RTL development for Xilinx FPGA's using Synopsys and Xilinx tools. Programming in Matlab, VBA and Verilog.

Graduation Date : Spring 2009

This was part of a MECOP assignment during my studies at OSU. the co-op covered two main projects. The first was to design a sensor system for detecting flickering in projector lamps. The second project was the design of a touch sensitive interface for projectors. This was a great internship and my first experience in a professional engineering environment.

MECOP (OSU) Junior Internship