Senior Ii R&D Engineer
This is a senior R&D engineering position, it requires a bachelors degree in Electrical Engineering and 5+ years experience working with ASIC design support. The main value added from this position is validation, characterization, and prototype development for SERDES IP, as well as taking a leadership role within an engineering team. The duties for this position cover a broad range of technical skills and tasks involved in supporting and debugging an ASIC design.The technical focus of this position is in ASIC IP for SERDES standards such as SATA Gen3, PCIe Gen3, and USB3.1 Gen2. Technical skills utilized include measurement and experimentation with of SERDES IP using lab equipment such as Lecroy SDA, Keysight JBERT, Keysight VNA. Other duties include RTL development for Xilinx FPGA's using Synopsys and Xilinx tools. Programming in Matlab, VBA and Verilog.
