Analog design for hardware stochastic neural network IC in TSMC 28nm tech using Cadence Virtuoso. Designed neuron consisting of noise generator, output activation function circuitry, and 60uA, 33GHz gain-bandwidth product amplifier. Developed 7 bit capacitive DAC used for synapse connections between neurons. Taped out chip in GF 14nm finFET tech that efficiently solves NP-hard problems that no current algorithm can solve efficiently in polynomial time.

Develop and update weekly labs for the course. Teach sections of the course to ensure course success.

Implemented new subcircuit topologies for high-speed sensing scheme aimed at reducing latency, increasing resolution, and minimizing mismatch with low power overhead. Created dashboard to visualize process parameters and their trends to expedite understanding of process benefits and drawbacks.

Oversee and teach lab sections of the course to ensure course success. Handle lab admin topics like lab policy as well as answer questions regarding lab content and debug circuits.

Worked in the Ethernet product line, learning about the Ethernet protocol and how PHYs work. Worked with US and German teams to write universal firmware used on all product EVMs, enabling chip identification and register access. Developed a parser to handle various inputs for a new application that enables quick debugging of chips. Conducted competitive analysis and updated data sheets and application notes to reflect changes made.