US Permanent Resident with over 20 years of professional scientific and engineering experience. Focused on discovering new and innovative solutions to the challenges of differentiated, quality semiconductor (CMOS) products and automated systems. Demonstrating leadership by working with executives (GMs, VPs, CTO), customers, industry partners and staff members to set up commercial programs (both scientific and engineering). This has included all phases of R&D - planning, budgets, schedules, hiring/staffing, funding, specifications, development, and commercial release. Areas have included diverse fields from FDA regulatory human clinical studies and robotics to commercial laboratories involving telecommunications and counter-terrorism. In addition, it has also allowed for development improvements in the field of high-speed serial PHY-layer technology used in CPUs, storage, and data-center fabrics using PCIe and CXL standards.Early scientific professional work to apply immunochemistry, robotics and pharmaceutical development to FDA regulated commercial labs. Responsible for applying fully articulated robotics, antibody based in-vitro assays, and photonic detection to human clinical applications in the 1990’s. Since early 2000's, focused on high-speed PCB and semiconductor (CMOS) development. Lead development initiatives and industrial collaborations in telecommunications (optical networks, wireless base-stations, cellular mobility – 5G NR/mmWave, 4G LTE, WiMax) and defense industry (security clearance). Within the last decade, the challenge has been on high performance server and data center CMOS products that run ever increasing workloads.Innovation in systems and product development. Tie together diverse areas of ASIC/FPGA, PCB, mechanical, firmware/software, and integration/architecture/design/verification for New Product Introduction (NPI). Specialties include:* High-speed RTL/PCB design/FPGA since 2005, covering various aspects of chip and circuit design/layout. Ultra high-speed IO & DAC/ADCs, PLLs, clock distribution trees, power, synthesizers.* Advanced verification for IP/ASIC/SoC (plan, schedule, lead, doc., code): ABV, efficient/scalable tests, coverage, simulation/regression, OVM/UVM, SystemVerilog, C++/OOP, APIs.* Performance benchmarks and modeling for high-speed, high-throughput CMOS products* System architecture – CXL fabrics, AXI-NoCs, embedded systems/firmware, multi-CPU SoCs and memory subsystems, security, DSP, DFx, error correction, modulation, baseband, and RF.