Stephan M. Email & Phone Number

Singapore

Team enabler, pioneer, innovator and problem solver.Working on ATE test roadmaps and concept improvements. Picking up trends and requirements to allow the test team moving forward into products of next technology node. Finding software and hardware solutions to reduce overall Cost of Test. Hands-on works when it comes to solving critical test issues, test escapes and deep dive debugs as well as test quality, yield and cost position improvements. Mentor and guide for other team members.

Singapore, Singapore

Principle ATE Test Lead of a team of engineers responsible to bring 16FFC Gateway products to volume market ramp. Conceptualizing and enabling test of future product derivatives. Developing test roadmap and infrastructure for next in line technology nodes.

Singapore, Singapore

Senior Staff ATE Test Lead of a team of engineers responsible for test program concept, development/debug, productive ramp and maintenance of wireline communication chips (Quadcore ATOM Gateway SOCs) in 16FFC

Singapore, Singapore

Senior Staff ATE Test Lead of a team of engineers responsible for test program concept, development/debug, productive ramp and maintenance of wireline communication chips (Quadcore ATOM Gateway SOCs) in 16FFC

Singapore, Singapore

Staff ATE Test Lead of a team of engineers responsible for test program concept, development/debug, productive ramp and maintenance of wireline communication chips (Gateway SOCs, Ethernet PHYs, ATOM subsystems) in C40 & 28nm

Singapore, Singapore

Staff ATE Test Lead of a team of engineers responsible for test program concept, development/debug, productive ramp and maintenance of wireline communication chips (Gateway SOCs, Ethernet & HSIO PHYs) in C65 & C40

Munich, Bavaria, Germany

Senior ATE Test Engineer for wireline communication chips (G.HN SOC, Ethernet PHY) in C65

Munich, Bavaria, Germany

Senior ATE Test Engineer for Design Library test chips (memories, standard cells, IOs, Efuses) in C11, L90, C65 & C40

Munich, Bavaria, Germany

ATE Test Engineer for Design Library test chips (memories, standard cells, IOs, Efuses) in C11, L90, C65 & C40

Bachelor Of Engineering - Be, Electrical, Electronics And Communications Engineering, 2.1

Bachelor Of Science - Bs, Electrical, Electronics And Communications Engineering, Second Class Honours