Senior Digital Design Verification Engineer
CurrentDesign Verification:- Working knowledge in SOC DV, GLS simulations, Security architectures - Experience with building scalable and reusbale testbenches- Automation frameworks for upgrading DV flows and reducing turn around time- IP verification using UVM - IP verification using Formal tools (JG SEC, FPV, SPV, CSR, CDC)Functional Safety : - Certified as a Functional Safety Engineer as per ISO26262:2018 (TUV SUD)- Experience in key Functional Safety aspects like Fault Injection, FMA , FMEDA , FSM etc. - Worked on Certifying multiple C2000 SoCs for ASIL-B/ASIL-D levels