Subhang Vempati Email and Phone Number

ASIC Developer | Digital Pre-Distortion (DPD) | EricssonI am an ASIC developer with expertise in digital pre-distortion (DPD) technology, currently working at Ericsson. Over the past 7 months, I have contributed to key projects in RTL design and verification, leveraging both hardware description languages and advanced EDA tools. My experience includes: Python Scripting: Developed automation scripts to generate RTL code from Excel-based register configurations, optimizing workflows and reducing manual effort. RTL Design: Led the conversion of the APB protocol from VHDL to SystemVerilog, improving system performance and modularity. EDA Tools: Hands-on experience with industry-standard tools such as Spyglass lint checker, Design Compiler, Cadence SimVision, and Questasim for simulation and verification.With a strong foundation in both hardware and software, I am passionate about driving innovation in ASIC design and delivering efficient, high-performance digital solutions.driving innovation in ASIC development and delivering high-performance, reliable digital solutions