As an R&D Manager at Cadence Design Systems, I lead a globally distributed team of engineers focused on next-generation performance optimizations for the Xcelium Logic Simulator—a high-performance, scalable solution for verifying complex system-on-chip (SoC) designs. I spearhead cross-functional collaboration to define the product roadmap, guiding architectural enhancements and streamlining development processes. My role involves designing innovative solutions to enhance team productivity and drive performance breakthroughs.As a Software Architect at Cadence, I oversee the design, development, and optimization of Xcelium. With over 8 years of experience in this capacity, I have co-authored several proprietary IPs in system software and core simulation technologies, delivering notable improvements in memory efficiency and runtime performance for our customers.I hold a PhD in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur, and have contributed to multiple publications and patents in the fields of data mining, parallel computing, and formal verification. A Senior Member of IEEE, I am actively involved in the research community. My current focus lies in developing cutting-edge methodologies, tools, and frameworks for simulation, machine learning, and compiler optimization. I am deeply passionate about solving complex technical challenges and creating innovative solutions that push the boundaries of simulation technology and verification.