As a spice modeling engineer, I worked on the development and support of SPICE model libraries for PDK enablement for the technology nodes ranging from 20nm to 0.18um. Worked on Logic, memory and High Voltage LDMOS devices.Responsibilities includes - characterization, parameter extraction (extraction includes IV,CV,Temp, Noise, leakage, STI, WPE and other LOD effects using BSIM, PSP and HISIM-HV models), Model QA, Performing statistical analysis on the ETest data obtained by measuring various wafers from different lots and generating mismatch and montecarlo models, Library development compatible to HSPICE and SPECTRE circuit simulators, Library QA using bench mark circuits, netlist preparations for circuit simulators. Also responsible for BJTs, Diodes and Passive device modeling using standard models and with VerilogA implementation.Also worked on interconnect simulations using field solver - raphael, for tech nodes ranging from 40nm to 0.18um. Responsibilities includes - development, maintaining the parasitic (capacitance/resistance ) databases for the BEOL profiles offerings of each tech node by the foundry, updating databases by aligning with changes made in the process.