Sudhir Shetty

Sudhir Shetty Email and Phone Number

Design Engineering Group Director @ Cadence Design Systems
Bengaluru, KA, IN
Sudhir Shetty's Location
Bengaluru, Karnataka, India, India
Sudhir Shetty's Contact Details

Sudhir Shetty personal email

About Sudhir Shetty

Hands-on Engineering leader and RTL IP design Engineer with 20+years of experience in roles involving overlap of Technical , Project Management , Talent Management and Leadership . The hardware design experience spans various design IPs of the Memory Subsystem (Memory PHY [LPDDR5X/GDDR6] and Memory Controller) and Serdes Subsystem (Serdes PHY [PCIE-GEN3] , PCS and higher layers of MAC,DL and TL layers). In addition, the early career experience in software development of developing enterprise level Distributed Banking Software imbibed a strong sense of design thinking , object oriented concepts ,various software architectures, system understanding and also helped gain knowledge of financial and accounting principles. Multiple experience of building and nurturing new RTL and Firmware design teams and leading new product development from concept to silicon : --People oriented , hands-on leadership - Passionate about mentoring and coaching engineers to fully realize one’s inherent potential and foster professional growth and development. --Process oriented - strong focus on quality designs with modularity , scalability and maintainability - Driving technical excellence and design quality by introducing design methodologies and best practices. --Frontend Architecture and Microarchitecture development --RTL design implementation and Functional Verification. --Experience of conceptualizing and developing Microcontroller based Hardware-Firmware co-design. --Experience of designing for Automotive Safety requirements. --Extensive depth in Design constraints development (SDC) and Timing Analysis and preempt physical design challenges. --Experience of collaborating closely with the cross-functional teams of Functional Verification, Mixed-signal Custom and Analog Design , DFT and Physical Design.--Experience of developing configurable IPs targeted for Personal Computing, Datacenter/Servers, Mobile and Automotive optimized for performance, power and area. --Manage project scoping and milestones, resource allocation and oversee execution to realize and lead time-to-market opportunity. --Talent and Growth management. --Supporting pre-sales customer engagements and post-sales customer enablement.

Sudhir Shetty's Current Company Details
Cadence Design Systems

Cadence Design Systems

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Design Engineering Group Director
Bengaluru, KA, IN
Website:
cadence.se
Employees:
10387
Sudhir Shetty Work Experience Details
  • Cadence Design Systems
    Design Engineering Group Director
    Cadence Design Systems
    Bengaluru, Ka, In
  • Cadence Design Systems
    Design Engineering Group Director
    Cadence Design Systems Jul 2024 - Present
    Bengaluru, Karnataka, India
  • Cadence Design Systems
    Director Of Design Engineering
    Cadence Design Systems Apr 2021 - Jun 2024
    Bangalore Urban, Karnataka, India
    --Established and nurturing a new PHY Frontend Design team of highly talented RTL and Firmware design engineers at Bangalore, India.--LPDDR5X PHY Frontend Design
  • Rambus
    Engineering Manager - Phy Logic Design
    Rambus 2004 - Apr 2021
    Bengaluru, Karnataka, India
    -Seeding a new RTL frontend design team for GDDR6 PHY development.-Pre-sales and Post-sales customer engagement for Technical discussions. -GDDR6 PHY Frontend design from scratch - first pass testchip silicon - first pass customer silicon - play central role driving architectural decisions, RTL design, drive overall phy clocking scheme, support foreplaning decisions, Design constraint development (SDC) and support STA , drive hierarchical timing analysis strategy covering the full PHY involving digital,custom-digital and analog block hierarchies, drive mixed signal block modelling and support functional verification, physical design, post-silicon validation and customer support.-High speed PCIE-GEN3 Serdes PHY development with HW-FW co-design.-Reusable Testchip platform development-Memory controller design-Verification of Memory controller-Verification of PCIE-GEN2 MAC ,DL and TL Layer-Validation of PCIE-GEN2 soft Layer (MAC/DL/TL) on FPGA platform for PCI-SIG certification
  • Growfast Computing Services
    Team Lead - Software
    Growfast Computing Services Nov 2000 - Aug 2002
    Mangalore, India
    Enhancements and maintenance of the Distributed Cash Management System for Leading Public Sector Bank. - Application of OOPS Concepts and Software Architectures on real-world software development - Usage of Relational database Systems - Financial Accounting Concepts - Development Language : Visual Basic 6. - RDBMS - Oracle .

Sudhir Shetty Skills

Verilog Asic Rtl Design Systemverilog Timing Closure Open Verification Methodology Semiconductors Pcie Static Timing Analysis Functional Verification Ic

Sudhir Shetty Education Details

Frequently Asked Questions about Sudhir Shetty

What company does Sudhir Shetty work for?

Sudhir Shetty works for Cadence Design Systems

What is Sudhir Shetty's role at the current company?

Sudhir Shetty's current role is Design Engineering Group Director.

What is Sudhir Shetty's email address?

Sudhir Shetty's email address is su****@****ail.com

What schools did Sudhir Shetty attend?

Sudhir Shetty attended Visvesvaraya Technological University.

What skills is Sudhir Shetty known for?

Sudhir Shetty has skills like Verilog, Asic, Rtl Design, Systemverilog, Timing Closure, Open Verification Methodology, Semiconductors, Pcie, Static Timing Analysis, Functional Verification, Ic.

Who are Sudhir Shetty's colleagues?

Sudhir Shetty's colleagues are Konstantin Rabkin, Pratika Chhatwal, Chihsuan Hung, Preetham B G, Bert Clewits, Sneha C, Dr. Claudia Roesch.

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