Sudarshan Sundar
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Sudarshan Sundar Email & Phone Number

Yield Enhancement @ Micron at Micron Technology
Location: Boise, Idaho, United States 13 work roles 2 schools
1 work email found @cornell.edu LinkedIn matched
✓ Verified July 2026 4 data sources Profile completeness 100%

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Current company
Role
Yield Enhancement @ Micron
Location
Boise, Idaho, United States
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Who is Sudarshan Sundar? Overview

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Sudarshan Sundar is listed as Yield Enhancement @ Micron at Micron Technology, a with 20793 employees, based in Boise, Idaho, United States. AeroLeads shows a work email signal at cornell.edu and a matched LinkedIn profile for Sudarshan Sundar.

Sudarshan Sundar previously worked as Yield Enhancement at Micron Technology and Product Development Engineer at Intel Corporation. Sudarshan Sundar holds Master Of Science - Ms, Materials Science And Engineering, 3.85/4 from Cornell University.

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{first}.{last}@cornell.edu
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Profile bio

About Sudarshan Sundar

Semiconductor professional with experience in Process Engineering, Yield Technology and Product Development

Listed skills include Microsoft Office, Nanotechnology, Matlab, Cad, and 32 others.

Current workplace

Sudarshan Sundar's current company

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Micron Technology
Micron Technology
Yield Enhancement @ Micron
boise, idaho, united states
Website
Employees
20793
AeroLeads page
13 roles

Sudarshan Sundar work experience

A career timeline built from the work history available for this profile.

Yield Enhancement

Current

Boise, Idaho, United States

NAND Product yield

Sep 2024 - Present

Product Development Engineer

Portland, Oregon Metropolitan Area

Global External Manufacturing & Sourcing

May 2024 - Aug 2024

Yield Analysis Engineer

Hillsboro, Oregon, United States

Technology Development Low Yield Analysis Engineer for next gen Intel transistors

Mar 2022 - May 2024

Process Technology Development Engineer

Hillsboro, Oregon, United States

TD Module &Integration Yield Engineer - Etch

Sep 2020 - Mar 2022

Graduate Student Researcher

Ithaca, New York Area

Masters Thesis (September 2018 - Present)High-Throughput Synthesis and Characterization of Metastable Materials:•Advanced high-throughput metrology & reliability of dielectric thin films deposited by Physical Vapor Deposition• Designed Photomask and developed liftoff process using photolithography for Platinum contact pads for probe measurements• Implemented Statistical process control to eliminate pinhole defects during capacitance cell device nanofabrication• Devised a mechanism for mapping metastable phases by validating with Spectroscopy, Optical Imaging and XRD

Aug 2018 - Aug 2020

R&D Product Development Engineering Intern

San Francisco Bay Area

• Improved SoC die attach assembly by implementing Statistical Process Control and Optical Metrology inspections• Resolved the reworkability of PCB Bonding film lamination in Flip-chip BGA packaging with Design of Experiments• Optimized MEMS probe spring metallurgy through SEM grain size estimation to withstand a million-lifecycle bend testing• Won the Most Innovative Poster Presentation Award during 'FormFactor Inc. Interns Poster Session Event 2019'.

May 2019 - Aug 2019

Nanofabrication & Characteriation Graduate Lab

Ithaca, New York Area

Hall Effect and Van der Pauw measurement:- Estimated Sheet Resistance, Sheet Carrier density, Electron mobility of Silicon wafer using 4 point measurement.- 'R' values were measured with 4*4 combinations of 'V' and 'I' to estimate the "Rs" value iteratively.- Hall effect measurement value of the sample is then calculated in the presence of a magnetic field.Contrast Curve Measurement using Photolithography:- Developed photoresist and inspected the resist thickness using Filmetrics, which measures filmthickness based on light interference.- Si wafer is coated with PR, soft baked and exposed methodically under UV lamp of determined intensity. - The curve is estimated with a semi-logarithmic plot of thickness Vs UV dosage. Hence, the slope is calculated.Fabrication and Characterization of MoS2 Thin Film Transistor :- Implemented dry transfer of MoS2 on PDMS stamp with the pre-patterned electrode using Photolithography- Devised 4-probe and output I-V characteristics (ID-VG), to obtain the ON-resistance of the FET with and without light

Jan 2019 - May 2019

Methods And Planning Engineer

Pune Area, India

Metallurgy Laboratory, Aluminum & Cast Iron Foundry:• Supervised the laboratory operations of Spectrometry and Mechanical testing as per ISO/TS 16949:2009 standards.• Inspected supplier materials quality during vendor visits to meet the World Class Quality (WCQ) standards.• Performed Failure analysis of rejected castings and implemented Action plans for defect control.• Implemented Six Sigma DMAIC Root Cause analysis using SPC, FMEA.• Achieved a lower castings rejection rate of Aluminum 3-ltr engine blocks from 38 to 3 percent towards March 2018, resulting in savings upwards of USD 80,000 per annum.

Aug 2017 - Mar 2018

Research Assistant

Chennai Area, India

Advanced High Strength Steels in the Automotive Industry:• Documented the novel heat treatment approaches on Automotive Steels as per the AHSS guidelines V5.0.• Designed the heat treatment cycle for Quenched partitioning treatment in the Gleeble 3800-GTC Thermo Mechanical Simulator (TMS).• Prepared study material on Automotive steels and their processing methods.

Jun 2017 - Jul 2017

Undergraduate Researcher

India

Mechanical behavior of Cu-Zn-Pb alloys upon Annealing and Severe Plastic Deformation : • Brass alloys of varying Pb concentrations were subjected to Annealing, followed by Mechanical testing and Route-A ECAP process.• Significant improvement in ductility was achieved but failure to undergo ECAP process was reported• Lead (Pb) segregation was identified upon EDS analysis using a HITACHI S-3000H electron microscope.• A technical paper on this study was presented at the 12th IRF International Conference at Goa,India (Sep 2017).

Jan 2017 - May 2017

Cleanroom Nanofabrication Intern

Singapore

(Singapore Pre-Graduate Award Fellowship, 2016)• Worked in Class 100 (ISO class 5) cleanroom.• Achieved controlled Molecular Beam Epitaxial growth of Ag thin film of 100 nm thickness at a rate of 2 nm/s on mica substrate by controlling process parameters of electron beam evaporation chamber.• Estimated the dielectric properties upon optical characterization using Ellipsometry and Spectrophotometry analysis in the UV-VIS wavelength range.• Characterized stable uniform epitaxial growth by electron microscope studies (SEM)

May 2016 - Aug 2016

Summer Research Intern

Polymer Nanocomposite Multiscale Modeling :• Synthesized Polydimethylsiloxane (PDMS) with Graphene Nanosheet reinforcement by Physical blend method.• Characterized stable dispersion interface using Quanta FIB Dual Beam SEM.• Simulated interfacial stress contours of tensile response in ABAQUS using the Mean field homogenization method.• Achieved 45 percent improvement in Elastic moduli upon dispersion

May 2015 - Jul 2015

In Plant Trainee

Testing of Advanced Composite materials :• Studied chemical analysis of polymer-clay composites using ICP optical emission spectroscopy, BrukerNMR and FTIR.• Additionally trained in failure analysis methods using bend test and torsion testing

May 2014 - Jun 2014
Team & coworkers

Colleagues at Micron Technology

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2 education records

Sudarshan Sundar education

Master Of Science - Ms, Materials Science And Engineering, 3.85/4

Activities and Societies:Spring 2019 Teaching Assistant: MSE 5150: Structures and Materials for Sustainable Energy Systems.

FAQ

Frequently asked questions about Sudarshan Sundar

Quick answers generated from the profile data available on this page.

What company does Sudarshan Sundar work for?

Sudarshan Sundar works for Micron Technology.

What is Sudarshan Sundar's role at Micron Technology?

Sudarshan Sundar is listed as Yield Enhancement @ Micron at Micron Technology.

What is Sudarshan Sundar's email address?

AeroLeads has found 1 work email signal at @cornell.edu for Sudarshan Sundar at Micron Technology.

Where is Sudarshan Sundar based?

Sudarshan Sundar is based in Boise, Idaho, United States while working with Micron Technology.

What companies has Sudarshan Sundar worked for?

Sudarshan Sundar has worked for Micron Technology, Intel Corporation, Cornell University, Formfactor Inc., and Cornell Nanoscale Science & Technology Facility.

Who are Sudarshan Sundar's colleagues at Micron Technology?

Sudarshan Sundar's colleagues at Micron Technology include Mark Helm, Chris C., Yi Tong Lin, Sunidhi Jain, and Roger Seow.

How can I contact Sudarshan Sundar?

You can use AeroLeads to view verified contact signals for Sudarshan Sundar at Micron Technology, including work email, phone, and LinkedIn data when available.

What schools did Sudarshan Sundar attend?

Sudarshan Sundar holds Master Of Science - Ms, Materials Science And Engineering, 3.85/4 from Cornell University.

What skills is Sudarshan Sundar known for?

Sudarshan Sundar is listed with skills including Microsoft Office, Nanotechnology, Matlab, Cad, Deform, Teamwork, Imagej, and Vic 2D.

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