Sujan Kasani Ph.D. Email and Phone Number
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• Currently working as Product development engineer responsible for the principal technical conduit between high volume production fabs and design division business groups, silicon validation groups, die prep/assembly/test, and other enabling organizations such as Intel's Corporate Quality Network, Corporate Planning, and Sales and Marketing. • In-depth knowledge in semiconductor physics , nano fabrication technologies, FDTD simulations on plasmonic nano structures, device testing & defect characterization of semiconductors and surface characterization of metal oxides and semiconductors.• Handled product development life cycle of server products like Xeon, Sapphire Rapids and Ponte Vecchio.• Tracking product health indicators and working with the fabs to drive yield improvements to ensure Intel is meeting or beating product health indicator goals.• Experience working in a high-volume state-of-the-art semiconductor manufacturing fab responsible for unit process development for technology nodes 7nm & 5nm.• Experience working in cleanroom environment, semiconductor nano fabrication, material evaluation for technology research and process development.• Knowledge in applying Statistical Process Control (SPC) technique with control charts to measure and analyze the variation in processes, controlled the product quality based on Design of Experiment (DOE).
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Product Development EngineerIntel Corporation Jan 2021 - PresentSanta Clara, California, Us• Monitors and controls work scope against the project plan, ensures effectiveness of the technology line and identifies risks and opportunities.• Ensure group work in compliance with safety and quality procedures. • Identify possible improvement opportunities and manage their implementation• Collaborate closely with FT Chair, Integration, DEFMET engineers and module R&D engineers, to devise and execute on the program priorities.• Provided Power/Performance guidance to the fabs and monitor performance vs expectations.• Lead engineer to handle Sapphire rapids product from NPI to production.• Run Ubit model to optimize binsplit buckets based on customer demand and power limitations.• Experience in reviewing product health and model synthesis based on recent product performance numbers.• Ensure the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp.• Analyze and evaluate component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability. -
Process EngineerIntel Corporation May 2019 - Jan 2021Santa Clara, California, Us• Responsible for leading scientific research enabling manufacture of innovative device architectures coupled with the realization.• Experience working on P1276/78 Dry Etch TEL process tools to meet 7/5nm technology process specifications. • Managed technicians team across a 7 shift – 24x7 manufacturing environment.• Owned disposition of etch parametric trends, tool station monitors, adaptive process control (APC), statistical process control system (SPC), and process control system (PCS). • Developed and optimized process conditions to obtain defect free parametrics to improve efficiency.• Investigate equipment failures to diagnose faulty operations and made appropriate maintenance recommendations. Documented and incorporated learnings into procedures to proactively address future equipment issues.
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Graduate Teaching AssistantWest Virginia University May 2018 - May 2019Morgantown, West Virginia, Us• Instructor for ‘Intro to Electrical Engineering’ course and ‘Electrical Circuits lab’ (EE 221 and 222). • Worked as a tutor for student athletes on Electrical Engineering and Physics courses.• Designed course work and lab projects. Reviewed course material with students one-on-one and in small groups.• Taught Ltspice simulation tool for analyzing digital & analog circuits and designed projects. • Mentored undergraduates in ‘Research Experience for Undergrads’ (REU) program by NSF. • Evaluated and graded assignments, examinations and lab reports. -
Phd Candidate, Graduate Research AssistantBio-Sensing, Bio-Imaging And Nano-Toxicity Lab, Wvu Jun 2015 - May 2019• Developed a novel fabrication process using NSL to fabricate large area gold coated Silicon nano ring array plasmonic substrate for Surface Enhanced Raman Scattering (SERS).• Analyzed optical/plasmonic properties of gold nano ring array with FDTD simulations (Optiwave FDTD).• Developed a point of care plasmonic biosensor for detection of miRNA.• Fabricated and studied plasmonic coupling behavior of quasi 3D nano structures. Analyzed optical cavity mode, which is tuned for enhanced biosensor detection using hybrid mode.
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Phd Candidate, Graduate Research AssistantSolar Energy Conversion Pec And Photo Voltaics Lab, Wvu Jun 2015 - May 2019• Expertise in FDTD simulations for tuning and analyzing plasmonic/optical properties of 3D nano structures for plasmon enhanced solar energy conversion efficiency. • Designed and developed p-n heterojunction (ZnO-CuO) photovoltaic cell and demonstrated improved solar energy conversion efficiency with incorporating plasmonic nanoparticles.• Fabricated and analyzed several 3D nano structures for light management for improved solar energy conversion efficiency in both photovoltaics and electrochemical cells.
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Cleanroom UserShared Research Facilities, Wvu Aug 2012 - May 2019* Nano fabrication process technologies, plasmonic and photonic device design and fabrication. *Thin film processing of Silicon and GaN.* Photolithography, Metal deposition (PVD & CVD), Dry and Wet etching and Annealing.* Processing equipment 1) Spin coating (Laurel technologies 400 spinner) 2)UV Lithography (Suss Microtech MA6 Aligner) 3)Flood exposure (OAI UV Flood exposure) 4)E-beam evaporation (BOC Temescal BJD-2000) 5)Sputter deposition(CVC 610DC Magnetron sputtering station) 6)Gold Wire Bonder (West Bond 74776E) 7)Rapid Thermal Processing (AnnealSys AS-Micro RTA) 8)Oxygen Plasma Asher (March PX-250 Plasma Asher). 9) E-beam evaporation (BOC Temescal BJD-2000, Kurt J Lekser LAB18) 10) Reactive Ion Etching (Trion Technology Minilock III RIE)* Characterization equipment1) Scanning Electron Microscope ( JEOL JSM-7600F)2) Stylus Profilometer ( Tencor Alpha-Step 200 )3) Optical Microscopy (Olympus BH-2 UMA)4) )Optical spectrum analyzer (Ocean optics USB 4000)5) Raman spectrum analyzer (iRaman plus B&W Tek6) Surface Photo Voltage (SPV)7) Deep Level Transient Spectroscopy (DLTS) 8)Atomic Force Microscope (Nanoscope, AFM)9) Hall effect measurements
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Graduate Research AssistantMaterial Growth And Characterization Lab (Mgcl),West Virginia University Aug 2012 - Dec 2014Morgantown, West Virginia, Uso Thin-Film processing of GaN LED.o Schottky Diode fabrication on both p-GaN and n-GaN.o Development of low contact resistive ohmic contacts and schottky contacts on p-GaN and n-GaN substrates.o Optimized pattering, baking and lift off processes.o SOIC Packaging is done on semiconductor devices for DLTS testing.EQUIPMENT MANAGER and PROCESS DEVELOPER• Optimized the photolithography process, soft bake time and temperature, UV light (365nm i-line) dosage, etch and metallization schemes for GaN LED, HEMT & Schottky diode fabrication.• Set up and maintained Capacitance-Voltage (CV) and Deep Level Transient Spectroscopy (DLTS) semiconductor characterizing tools.
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Project InternMultisensor Manipulation Module (Msmm), Wvu & Wv Robotic Technology Center, Nasa Aug 2012 - Dec 2014• Hands on experience on vacuum and low temperature systems.• Experienced in analyzing the C-V and DLTS signals for quantifying doping concentration, activation energy of traps, and traps concentration of group III-V semiconductors.• Maintained communication between growth and characterization groups for GaN purity feedback.
Sujan Kasani Ph.D. Skills
Sujan Kasani Ph.D. Education Details
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West Virginia UniversityElectrical Engineering -
West Virginia UniversityElectrical Engineering
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Andhra UniversityElectronics And Communications Engineering
Frequently Asked Questions about Sujan Kasani Ph.D.
What company does Sujan Kasani Ph.D. work for?
Sujan Kasani Ph.D. works for Intel Corporation
What is Sujan Kasani Ph.D.'s role at the current company?
Sujan Kasani Ph.D.'s current role is Product Development Engineer at Intel Corporation.
What is Sujan Kasani Ph.D.'s email address?
Sujan Kasani Ph.D.'s email address is su****@****tel.com
What is Sujan Kasani Ph.D.'s direct phone number?
Sujan Kasani Ph.D.'s direct phone number is +130429*****
What schools did Sujan Kasani Ph.D. attend?
Sujan Kasani Ph.D. attended West Virginia University, West Virginia University, Andhra University.
What are some of Sujan Kasani Ph.D.'s interests?
Sujan Kasani Ph.D. has interest in Photography, Coding, Playing Cricket, Gadgets.
What skills is Sujan Kasani Ph.D. known for?
Sujan Kasani Ph.D. has skills like Electron Beam Evaporation, Deep Level Transient Spectroscopy, Sputter Deposition, Photolithography, Originlab, Ni Labview, Matlab, Rapid Thermal Annealer, Wire Bonding, Tsupreme, Thin Films, Characterization.
Who are Sujan Kasani Ph.D.'s colleagues?
Sujan Kasani Ph.D.'s colleagues are Hao Wu, Solomon Habtemariam, Anthony Ngo, Brendan Rhoan, Mba, Helen Liu, Ying Jin, Kapil Wadhera.
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