Sumit Kumar Mishra Email & Phone Number

– Working as a Synthesis and STA Engineer at Core Integration and STA team which mainly focused on the Quality of Gate-level Netlist and its PPA issues.– Till now, I have completed two projects, In the first project, I worked on a mid-range mobile processor of 3nm core design and handled hard Marco block integration which was always on block passing supply to other blocks when the main supply was switched off.– In the Second Project I worked on 2nm technology and handled 2 blocks parallelly which was a timing-critical block so the good floorplan was a bit challenging.– Experienced in handling real physical synthesis for designs close to 1.5M instance count– knowledge of debugging and fixing issues in SDC, and UPF generation.– Basic timing analysis using easy time, PPA Analysis and optimization techniques, Quality checks like ERC, DRC, CLP, preSTA, LEC, CTS Sanity and various DFT checks, Detailed Floorplan DEF analysis.– Knowledge of concepts of STA (MCMM, AOCV, OCV, CRPR) fixing setup and hold timing violations.Handling RTL linking issues, feedback on SDC to the Design Engineer, RTFF synthesis, DFT insertion according to the scan plan, and analysing DFTDRC violations. Run, analyze, debug and fix compression stuck and transition test coverage.* 9.5 months internship experience at STMicroelectronics, Noida. Having experience in the charge pump, operational amplifier design, simulation, and layout, I also understand flash and other memory and working with their array structure at CMOS90D technology.- Strong fundamental knowledge of Analog electronics, digital electronics, circuit theory, and control systems.- Knowledge of basics of programming languages like c, c++, Verilog, and Basic system Verilog.- Also familiar with CAD tools like Xilinx Vivado, synthesis, RTL design, and Physical design flow.