Sumit Ahuja Email & Phone Number

Santa Clara, Ca, Us

Santa Clara, Ca, Us

Consistence track record in delivering ASICs for diverse domains such as networking, CPU, GPU.- Ability to work in a dynamic work environment in both IP and SoC products; aided by strong fundamentals in comp arch including CPUs, caches, memory subsystem, design/architecture flows.- Extensive experience in early stage performance/power studies, architecture modeling, micro-arch changes for timing/power/wiring-congestion, post-silicon performance/functional debug.- Team player and experience with mentoring interns, full-time employees.- Strong background in optimizing memory sub-system performance for Deep learning applications.

Santa Clara, California, Us

worked on low power/area related micro-architecture optimization for next-generation Intel architecture (IA) based microprocessor. Hands-on experience with power, performance modeling using high-level simulators. I have explored all the aspects of the design process, starting from micro-architecture, RTL development, Formal verification, power estimation, reduction. I have also interfaced with back-end engineers for timing closure, clock-tree synthesis, place, and route.

San Jose, Ca, Us

Worked on micro-architecture of fragmentation and reassembly module starting from putting in micro-architectural pipeline stages, working on RTL development and interfacing with formal verification team to get design formally verified. I also developed and maintained RTL development for statistics unit block and chip to chip interface using serdes for the system. I developed power estimation and reduction methodologies for the data forwarding engine for an ASIC for packet switching (for networking applications).

I worked towards reducing the power consumption of hardware generated by C2R (HLS tool of Cebatech Inc.). My responsibilities include proposing and researching the power reduction technique(s) and implementing it. I helped in implementing and designing sequential clock-gating, advanced clock-gating based power reduction techniques.

Involved in implementing the power optimization features for the high-level synthesis for C2R compiler. I mainly worked on the power optimization feature for C2R compiler, technique involves register power reduction at high-level such that generated hardware consumes less power. I also worked on the mehodology that can connect the C2R output seemlessely to ASIC/FPGA flows for power optimization purposes.

Santa Clara, California, Us

Worked on various projects including test generation for peak power and test generation for model driven system validation.

Us

Worked on several methodologies related to power estimation and reduction such as power-gating flow using physical studio, RTL power estimation flow development using power theater. Power reduction using power artist. I also developed power estimation flow for several customers (companies) using PowerTheater in US, Korea, Japan, Israel and India.

Phd, Vlsi/Eda For Low Power

M.Eng, Digital Circuits And Systems.

B.Tech, Electrical

Education record