Senior Memory subsystem Architect at NVIDIA. Currently, I am focusing on optimizing GPU memory subsystem performance for Deep learning applications. In the past, I've worked on micro-architecture and design of CPU memory subsystem. I've designed Load Store Unit, L2$, developed proposals for interactions among cache hierarchies, cache state handling, etc. I've also designed/implemented data$ prefetchers, control logic for caches (L1, L2), coherency, snooping and TLB interactions related issues. I've lead design teams and mentored interns and full-time employees. I've worked on various different stages of ASIC design process including ECOs and lab bring up.My academic background includes experience with statistical modeling, machine learning, and deep learning algorithms/design.Profile Summary: -Consistence track record in delivering ASICs for diverse domains such as networking, CPU, GPU.- Ability to work in a dynamic work environment in both IP and SoC products; aided by strong fundamentals in comp arch including CPUs, caches, memory subsystem, design/architecture flows.- Extensive experience in early-stage performance/power studies, architecture modeling, micro-arch changes for timing/power/wiring-congestion, post-silicon performance/functional debug.- Team player and experience with mentoring interns, full-time employees.- Strong background in optimizing memory sub-system performance for Deep learning applications.