STA-PD Engineering Manager for LPDDR DDR-PHY’s. • Expertise in Timing closure for high speed DDRPHY designs.• Responsible for complete backend activities of PHY development. Lead the team comprising of Floorplan, PnR and signoff activities for multiple projects.• Worked with design teams to come up with strategies for timing closure of high frequency DDRPHY blocks• DDRPHY is a unique IP which multiple stake holders (packaging, analog IP, circuit simulation etc) . Worked with inter-disciplinary teams to achieve best PPA.

STA-PD Lead for LPDDR DDR-PHY's • Lead the team comprising of Floorplan, PnR and signoff activities for multiple projects.• Worked on FloorPlan and PnR for the complex high speed LPDDR4 cores.• Did Floor planning for the LPPDR5 DDRPHY’s to achieve best PPA’s even when non-scaling area trend was observed in prior chips• Worked with Design teams also to provide them feedback on design updates.

STA Lead for LPDDR DDR-PHY's. Worked on multiple Generations of LPDDR.• Work with Physical Designers to come up with FloorPlan, Placement and CTS specs to meet Timing and complex skew and latency checks that are part of DDR Protocol• Work with Designers for Pre-Layout timing and for constraints validation/cleanup.• Worked on STA Convergence of multiple blocks of DDR PHY which includes the standard min,max,Timing DRC’s,Noise etc. DDR PHY also has skew checks and latency checks for the protocol to work, came up with scripts for newer Gen DDRPHY’s.• Created a Wrapper around the STA environment to make the regression faster and independent of user. This is used to run, collate the reports. This is being used by DDR PHY IP teams across globe in QCOM.• As STA lead for many Projects have successfully TO’ed ~10 Chips in 2 years without having a Timing issue in Silicon. Have handled multiple projects in parallel with my team• Trained Juniors in the DDR IP team in the field of STA.

STA Engineer for SoC Level and Block Level • Worked on Pre-Layout Timing to provide feedback to Designers for quality of the Synthesis• Worked with Physical Design Teams both Block Level and Top Level to come up with CTS spec.• Created Wrapper around the STA environment so that Block Owners without any STA knowledge can run STA for Blocks and generate ECO’s• Worked on SoC Level Timing Convergence.

Responsible for analyzing pre-layout and post-layout timing, develop timing ECOs and leakage recovery ECO’s, and work closely with layout engineers to achieve timing closure.Responsible for Power analysis and leakage current calculation of the SoC to be provided to tester teams. Work includes analysis of peak power, averaged power and leakage power, working with Verification/DFT to achieve power targets