Sunni S. Email & Phone Number

I am a dedicated VLSI Engineer with a Master's degree in Integrated Sensor Systems (VLSI) from IIT Hyderabad. Currently pursuing Advanced Training in Digital Design and Verification from Maven Silicon, I excel in ASIC/FPGA design, RTL Design and Verification, digital electronics, and programming languages like Verilog HDL, System Verilog, UVM and C/C++. I am adept at using EDA tools like Xilinx Vivado FPGA, Mentor Graphics - Questasim, and Xilinx ISE.Projects:Router 1x3 – RTL Design and Verification• Architected the block level structure for the design for router that accepts data packets on single 8-bit port and routes them to one of the three output channels channel0, channel1, channel2.• Implemented RTL using Verilog HDL.• Verified the RTL model using Verilog Test BenchImplemented a SV Test Bench on MOD12 synchronous counter:• Designed a mod12 synchronous mod12 loadable counter• Verified the design using System Verilog Test Bench ArchitectureDesigned a 64kB RAM and verification using system Verilog Test Bench:• Implemented RTL for 64kB RAM• Verified the design using System Verilog Test Bench Architecture I am eager to leverage my skills and knowledge in a dynamic and challenging environment where I can contribute to cutting-edge projects in digital design and verification. Let's connect and explore opportunities to collaborate and innovate in the world of VLSI engineering.

• 

  Trainee

  Maven Silicon

  Jan 2024 - Present - Bengaluru, Karnataka, India

  Training on : Advanced Digital Circuits, Verilog HDL, Verification Using System Verilog and UVM, Static Timing Analysis, Code Coverage, Functional Coverage