Supratim Basu Email and Phone Number

Experienced professional with a demonstrated history of working in the ASIC physical design field with complex SoC designs. 15+ yrs of experience in industry to implement RTL-GDS flow at various technology nodes including 10nm FinFET and below. ASIC physical design flow including placement and optimization, route, congestion analysis/debug, Clock Tree Synthesis (CTS), custom multi-source CTS, MMMC and Multi-clock domain timing closure, Signal Integrity, Physical Verification (DRC/LVS), Conformal Low Power (CLP), IR-drop/EM analysis, Formal Verification, Sign-off timing analysis, etc.Specialized in congestion analysis and implementation of crossbar switches and bus routing. Expert in data flow and parametric analysis of the design.COMPLEXITY HANDLED:o 40M std cell gate hierarchical top level design.o Physical verification lead for a giant chip (~650mm2, 209M std cell gate count, 162 RAM bits).o SI/Crosstalk aware routing methodology for crosstalk avoidance.o 4M gate (std cell only) / 200+ macro block implementation.o High speed clock (3.69 GHz) with complex multi-clock design - analysis and optimization.o Hand-crafted CTS for top level.o PPA implementation on hierarchical and flat design.CUSTOM FLOW HANDLED:o SERDES/ mixed signal integration and interface custom routing.o Custom routing with ESD requirements for ESD clamp/diode.o Half-bump integration: sharing digital logic area under bump powered by isolated voltage domain like analog signal, etc.o Customized IO Ring to reduce the die size for a Multi-Chip Module (MCM) chip.o Top-down and Bottom-up approach for timing budget and physical design convergence.FULL CHIP:o Partitioning, pin assignments for standard and Multi-Instantiated Modules (MIM), die size estimation.o Feedthrough and scan path planning, Macro placement with Data Flow Analysis (DFA),o IO / Bump planning between voltage islands.o Creating foundry delivery kit. Package interface, handoff data to substrate team.