Digital Design Engineer
Current- Design for test lead for product segment producing high voltage power converter ICs forindustrial and automotive applications, directly responsible for all DFT related design activitiesin the product, namely DFT.
- Extensively used Siemens Tessent tools for ATPG generation for both compressed and uncom-pressed scan chains using varied fault models (stuck-at, IDDQ, Transition, Cell aware etc)
- Applied IJTAG protocol (IEEE 1687) and JTAG protocol (IEEE 1149) controlling the product in testmode. Developed ICL/PDL descriptions of tests, which are simulated using gate level netlist.
- Have successfully led contractors for taping out several derivative products, overseeing andcoaching them on ATPG activities undertaken.
- Involved in several innovation activities and learnings including TKLBIST, Kaleidoscope andPower Artist.
- Gained proficiency in using industry standard tools for ASIC development, including CadenceXcelium, HAL and internal company tools for DFT activities.