Susan Tran Email and Phone Number
Susan Tran work email
- Valid
- Valid
- Valid
Susan Tran personal email
- Valid
- Valid
- Valid
- Valid
- Valid
- Valid
- Valid
• Over 15 years of experience in Processor, Asic and SoC Design Verification.• Involved in all Design Verification stages including specifications, architecture implementation of simulation environment, testbench, testplan, and executing Verification process for complex ASIC’s.• Led verification efforts on complex networking ASIC projects from concept until completion. • Strong problem solving skills. Independently handled the project.• Experienced in developing verification infrastructure, test-bench using Verilog, System Verilog, UVM, OVM verification methodology.• Lead verification efforts on complex PCIe-SRIOV, PCIe-DMA, PCIe-Memory Bridge from block level to system level in simulation. • Knowledge of PCIe, PCIe-SRIOV, Memory Interface, DMA, Packet processors, Routing, Switching, Optical and Ethernet interface.• Lead SoC verification efforts on Intel Compute Express Link (CXL) protocol.
-
Design Verification Sr. Member Of Technical StaffIntel Corporation Jun 2012 - PresentSanta Clara, California, UsAs a design verification technical lead and member of technical staffs, I have been leading verification efforts for multiple PCIe and CXL related projects from concept to completion.• Lead Asic and SoC verification efforts on Intel Compute Express Link (CXL) protocol.• Lead, own, and drive verification for multiple PCIe products such as PCIe-SRIOV, PCIe-DMA, and PCIe-Avalon Memory Bridge.• Responsible for UVM System Verilog test bench, test plan, coverage, execution, and regressions• Lead verification efforts for multiple projects from block level to full chip level.• Developed drivers, monitors, checkers, scoreboards, environments in UVM System Verilog to use in block and full chip level• Lead and implement PCIe system level verification test bench using Synopsys PCIe-VIP, Avery PCIe-VIP• Implement UVM sequences and tests at block and chip level• Develop Perl and Shell scripts to run simulation, launch and check regressions, coverage reports, and automate simulation process• Lead, implement, and support common verification run scripts to use cross multiple projects • Triage and debug of regression failures -
Design Verification Lead & Principle EngineerRambus Inc Sep 2011 - Jun 2012Lead and establish verification environment using system verilog and OVM methodology. Responsible for define verification methodology, environment infrastructure, and architect verification test bench for test chips, fpga. Familiar with system verilog OVM and UVM verification methodology.
-
Design Verification LeadCisco Sep 2000 - Jul 2011San Jose, Ca, UsAs a Design Verification Lead, was responsible for multiple Asic verification:• Defined and implemented Asic design verification environment, drivers, checkers, monitors, behavioral models, and test cases in Vera, VMM, System Verilog to verify Asics for Optical, Ethernet, Fabric interface, and Packet Processor• Responsibilities include defining test bench architecture, test environment, drivers and checkers development, functional test plans, directed tests and random tests implementation. • Support design verification process such as running simulation, debugging, bug tracking, random regression• Led and played key role on team that established verification infrastructure using VMM methodology, System Verilog, SVA, and design verification coverage methodology. Also, led, defined, and implemented test bench, test plans, and verification process for six of Cisco Asics, and Fpga. • Defined, implemented DV test bench components to verify Asics from block to full chip level. Developed random and directed tests, together with coverage to verify Asics and Fpga• Supported design verification process such as building scripts, Makefiles, running simulation, debug, regression.• Familiar with PCI Express, Packet Processing, Packet Scheduler, Link List, EIO, Serdes, SPA, System Verilog, Vera-NTB, VMM. -
Design Verification LeadCom21 Inc May 1997 - Sep 2000• Defined, implemented, and supported Asic design verification for Cable Modems and Headends from RTL to gate level. • Responsibilities include defining test bench architecture, test methodology, test environment, model development, functional test plans, and directed tests implementation. • Executed and supported design verification process such as running simulation, debugging, bug tracking.Familiar with Memory Interfaces, Uarts, Interrupts, Timers, Controllers, CPUs and Peripherals, PCI Interfaces, Perl and C Shell scripts, and Data Over Cable Specifications.
-
Design Verification EngineerSamsung Semiconductor Inc Mar 1996 - May 1997• Developed, executed, and supported system design verification for Multimedia Signal Processor (MSP) project. • Responsibilities include developing test methodology, test plans, writing diagnostic tests and test cases in ARM and vector processor assembly language.• Triaged and debugged regressions, and supported design verification process from RTL to gate level. -
Design Validation EngineerIntel Corporation Jan 1992 - Mar 1996Santa Clara, California, Us• Developed tests cases to verify the functional and critical path of Pentium micro-processor. Responsible for writing test program in 486/Pentium assembly language programming.• Developed, executed, and supported Pentium CPU design verification/validation, test programs, and sort data analysis. • Responsibilities included developing test methodology, test plans, test process, and also managing and providing qualified Pentium test programs to Intel factory. Test programs were written in C using Schlumberger ASAP and systems.
Susan Tran Skills
Susan Tran Education Details
-
University Of California, BerkeleyElectrical Engineering And Computer Science
Frequently Asked Questions about Susan Tran
What company does Susan Tran work for?
Susan Tran works for Intel Corporation
What is Susan Tran's role at the current company?
Susan Tran's current role is Sr. Member of Technical Staff Design Verification at Intel.
What is Susan Tran's email address?
Susan Tran's email address is st****@****era.com
What schools did Susan Tran attend?
Susan Tran attended University Of California, Berkeley.
What skills is Susan Tran known for?
Susan Tran has skills like Solution Selling, Collaboration Building, Infrastructure, Training And Development, Sales, Perl, Functional Verification, Cost, Management Software, Jive, Processors, Dve.
Who are Susan Tran's colleagues?
Susan Tran's colleagues are Dung Nguyen, Jia Yan Go, Brian H., Sanaa Parvin, 李建华, Ofer Zimmerman, 吴传强.
Free Chrome Extension
Find emails, phones & company data instantly
Aero Online
Your AI prospecting assistant
Select data to include:
0 records × $0.02 per record
Download 750 million emails and 100 million phone numbers
Access emails and phone numbers of over 750 million business users. Instantly download verified profiles using 20+ filters, including location, job title, company, function, and industry.
Start your free trial