CSCE 616 - Introduction to Hardware Design Verification

Conducted formal verification of PSM Sequencer block using JasperGold, ensuring reliable power management by controlling CPU voltage rails.Developed and implemented rigorous checkers and assumptions for comprehensive functionality validation. Enhanced expertise in formal verification techniques, RTL design, and handshake protocols.Developed a Python script to generate a coverage file, ensuring that specific register fields are randomized with non-Power-On-Reset values.

My primary responsibilities included verification of power management, Clock Control, and Debug-related features.Verification of Clock Management Unit (involving Clock Throttling, Limit Management features, PLL Initialization, PLL characterization, and PLL stabilization). Designed a PLL Transactor that mimics the behavior of actual RTL, which helps to reduce simulation time and ease the verification process.Verification of Dynamic Clock and Voltage Scaling (DCVS) (a… Show more My primary responsibilities included verification of power management, Clock Control, and Debug-related features.Verification of Clock Management Unit (involving Clock Throttling, Limit Management features, PLL Initialization, PLL characterization, and PLL stabilization). Designed a PLL Transactor that mimics the behavior of actual RTL, which helps to reduce simulation time and ease the verification process.Verification of Dynamic Clock and Voltage Scaling (DCVS) (a power management technique whereby the voltage and frequency can be scaled to maximize energy-efficiency while providing peak performance levels).Reliability Counter Verification - A feature that determines the reliability of the CPU by calculating for how long is a particular core up and running with the particular frequency and voltage.Running Connectivity Checks for Thermal Sensors and running and monitoring regressions with the design changes. Show less